公开(公告)号：US06573167B2

公开(公告)日：2003-06-03

申请号：US09921119

申请日：2001-08-02

申请人： Guoqiang Xing ,  Wei-Yung Hsu ,  Changming Jin

发明人： Guoqiang Xing ,  Wei-Yung Hsu ,  Changming Jin

IPC分类号： H01L2122

CPC分类号： H01L21/0332 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32139 ,  H01L27/1085 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： A carbon hardmask (122) for etching hard-to-etch materials (110/112/114) such as Pt, Ir, Ru, IrO2, RuO2, BST, PZT, SBT, FeNi, and FeNiCo and other used in DRAMs, FeRAMs, and magnetic storage devices. Chemically assisted physical sputter etching using argon and limited or no oxygen may be used to etch the hard-to-etch materials (110/112/114) with high selectivity to the carbon hardmask (122).

公开(公告)号：US06323553B1

公开(公告)日：2001-11-27

申请号：US09417586

申请日：1999-10-14

申请人： Wei-Yung Hsu ,  Qi-Zhong Hong

发明人： Wei-Yung Hsu ,  Qi-Zhong Hong

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/76882

摘要： A new liner structure and method to incorporate this liner into process flows in order to lower the processing temperature of aluminum extrusion or reflow cavity filling. The structures produced by this innovative method are particularly useful for advanced sub-quarter micron multi-level interconnect applications.

摘要翻译： 一种新的衬里结构和方法，将该衬管结合到工艺流程中，以降低铝挤压或回流填充的加工温度。 通过这种创新方法生产的结构对先进的二分之一微米多级互连应用尤其有用。

公开(公告)号：US06184129B2

公开(公告)日：2001-02-06

申请号：US09405265

申请日：1999-09-23

申请人： Ming Hwang ,  Jiong-Ping Lu ,  Duane E. Carter ,  Wei-Yung Hsu

发明人： Ming Hwang ,  Jiong-Ping Lu ,  Duane E. Carter ,  Wei-Yung Hsu

IPC分类号： H01L2148

CPC分类号： H01L27/10873 ,  H01L21/28061 ,  H01L21/76885 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/4941 ,  H01L29/66545

摘要： A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon (66) with a sacrificial material (68), is disclosed. Gate sidewalls (70) are created to protect the sides of the polysilicon (66) and the sacrificial material (68), followed by stripped the sacrificial material (68) to expose the top surface of the polysilicon (66). Next, a diffusion barrier (76) is deposited over the exposed polysilicon (66) and a metal layer (78) is selectively grown on the diffusion barrier (76) to form a gate contact and conductor. Finally, a dielectric layer (80) is deposited over the selectively grown metal layer (78), the sidewalls (70) and the gate oxide (64).

摘要翻译： 公开了一种用于制造低电阻率多金属硅化物导体/栅极的方法，包括以下步骤：在栅极氧化物（64）上形成多晶硅（66），随后用牺牲材料（68）保护多晶硅（66）。 产生栅极侧壁（70）以保护多晶硅（66）和牺牲材料（68）的侧面，随后剥离牺牲材料（68）以暴露多晶硅（66）的顶表面。 接下来，在暴露的多晶硅（66）上沉积扩散阻挡层（76），并且在扩散阻挡层（76）上选择性地生长金属层（78）以形成栅极接触和导体。 最后，介电层（80）沉积在选择性生长的金属层（78），侧壁（70）和栅极氧化物（64）上。

公开(公告)号：US6143645A

公开(公告)日：2000-11-07

申请号：US16118

申请日：1998-01-30

申请人： Wei-Yung Hsu ,  Qi-Zhong Hong

发明人： Wei-Yung Hsu ,  Qi-Zhong Hong

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76882

摘要： An integrated circuit fabrication method for filling a high-aspect-ratio via with a metallization layer wherein there is provided a dielectric layer having a via therein. A wetting layer is deposited over the dielectric layer and within the via and the via sidewalls, the wetting layer being of a material which lowers the melting temperature of the metallization when combined with the metallization. The metallization layer is deposited over the wetting layer and the via but not completely filling the via with the metallization. The wetting agent with metallization thereon are heated to a temperature below the melting temperature of the metallization, the temperature being sufficient to cause the wetting layer to combine with the metallization, lower the melting temperature of the metallization to the temperature or below the heating temperature to cause the metallization to flow and fill the via. A diffusion barrier layer can be provided on the wetting layer over horizontal portions of the dielectric layer, but not on the wetting layer at sidewalls of the via.

摘要翻译： 一种用于通过金属化层填充高纵横比通孔的集成电路制造方法，其中提供了其中具有通孔的电介质层。 润湿层沉积在电介质层上并且在通孔和通孔侧壁内，润湿层是当与金属化组合时降低金属化的熔融温度的材料。 金属化层沉积在润湿层和通孔上，但不完全用金属化填充通孔。 将其上具有金属化的润湿剂加热到低于金属化的熔融温度的温度，该温度足以使润湿层与金属化组合，将金属化的熔融温度降低至温度或低于加热温度至 导致金属化流动并填充通孔。 扩散阻挡层可以在介电层的水平部分上的润湿层上提供，而不在通孔的侧壁处的润湿层上。

公开(公告)号：US6037013A

公开(公告)日：2000-03-14

申请号：US34269

申请日：1998-03-04

申请人： Wei-Yung Hsu ,  Qi-Zhong Hong ,  Jiong-Ping Lu

发明人： Wei-Yung Hsu ,  Qi-Zhong Hong ,  Jiong-Ping Lu

IPC分类号： H01L21/285 ,  H01L21/318 ,  B05D3/06 ,  C23C16/30

CPC分类号： H01L21/3185 ,  H01L21/28568

摘要： A barrier/liner structure (10) and method. First, a porous nitride layer (12) is formed over a structure (18), for example, by metal-organic CVD (MOCVD). Then, the porous nitride layer (12) is exposed to a silicon- (or dopant-) containing ambient to obtain a silicon-(or dopant) rich surface layer (14). Finally, the silicon- (or dopant) rich surface layer (14) is nitrided to obtain a silicon-nitride (or dopant-nitride) enriched surface layer (16).

摘要翻译： 屏障/衬垫结构（10）和方法。 首先，例如通过金属 - 有机CVD（MOCVD）在结构（18）上形成多孔氮化物层（12）。 然后，多孔氮化物层（12）暴露于含硅（或掺杂剂）的环境中以获得富含硅（或掺杂剂）的表面层（14）。 最后，将富含硅（或掺杂剂）的表面层（14）进行氮化，以获得富含氮化物（或氮化物）的表面层（16）。

公开(公告)号：US5892282A

公开(公告)日：1999-04-06

申请号：US757776

申请日：1996-11-27

申请人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

发明人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

摘要： Methods are provided for the construction of metal-to-metal connections between non-adjacent layers in a structure, such as a semiconductor device. A first metal conductor layer is provided along a substrate. An anti-reflection cap is provided in overlying relation with said first conductor layer. At least a portion of the dielectric layer and the anti-reflection cap is removed to define a passage which extends from an upper surface of the dielectric layer to the first metal conductor. The passage is substantially filled with a fill metal, and a second metal conductor layer is applied over at least a portion of the dielectric layer and the substantially filled passage to electrically connect the first and second metal conductors. A diffusion liner can optionally be applied to the passage prior to application of the fill metal. The passage fill metal and second conductor layer can be integrally formed, and the fill metal and at least one of the conductor layers are formed from the same matrix metal.

摘要翻译： 提供了用于在诸如半导体器件的结构中的非相邻层之间的金属 - 金属连接的构造的方法。 沿着基板设置第一金属导体层。 防反射盖以与所述第一导体层重叠的关系提供。 去除介电层和防反射盖的至少一部分以限定从电介质层的上表面延伸到第一金属导体的通道。 通道基本上填充有填充金属，并且第二金属导体层被施加在电介质层和基本上填充的通道的至少一部分上以电连接第一和第二金属导体。 在施加填充金属之前，扩散衬垫可以可选地施加到通道。 通道填充金属和第二导体层可以一体地形成，并且填充金属和至少一个导体层由相同的基体金属形成。

公开(公告)号：US08012000B2

公开(公告)日：2011-09-06

申请号：US11695484

申请日：2007-04-02

申请人： Yuchun Wang ,  Robert A. Ewald ,  Wei-Yung Hsu ,  Liang-Yuh Chen

发明人： Yuchun Wang ,  Robert A. Ewald ,  Wei-Yung Hsu ,  Liang-Yuh Chen

IPC分类号： B24D11/02

CPC分类号： B23H5/08

摘要： A method and apparatus for extending a polishing article lifetime on a polishing tool with multiple platens is described. The apparatus includes an advanceable roll to roll platen with multiple embodiments of a polishing article to be used thereon. The polishing article is adapted to perform a polishing process by removing conductive and dielectric material from a substrate while minimizing downtime of the polishing tool. In some embodiments, the polishing article may be a dielectric material or a conductive material and is configured to include a longer usable lifetime to minimize replacement and downtime of the tool.

摘要翻译： 描述了一种用于在具有多个压板的抛光工具上延伸抛光制品寿命的方法和装置。 该设备包括具有可在其上使用的抛光制品的多个实施例的可推进的辊对辊压盘。 抛光制品适于通过从衬底移除导电和电介质材料，同时最小化抛光工具的停机时间来执行抛光工艺。 在一些实施例中，抛光制品可以是介电材料或导电材料，并且被配置为包括更长的可用寿命以最小化工具的更换和停机时间。

公开(公告)号：US20100130101A1

公开(公告)日：2010-05-27

申请号：US12621376

申请日：2009-11-18

申请人： YUCHUN WANG ,  Long Cheng ,  Kuo-Lih Chang ,  Wei-Yung Hsu ,  Wen-Chiang Tu

发明人： YUCHUN WANG ,  Long Cheng ,  Kuo-Lih Chang ,  Wei-Yung Hsu ,  Wen-Chiang Tu

IPC分类号： B24B49/04 ,  B24B49/10 ,  B24B49/12 ,  B24B57/02

CPC分类号： B24B37/042 ,  B24B49/10 ,  B24B49/12 ,  B24B57/02

摘要： Embodiments described herein provide a method for polishing a substrate surface. The methods generally include storing processing components in multiple storage units during processing, and combining the processing components to create a slurry while flowing the processing components to a polishing pad. A substrate is polished using the slurry, and the thickness of a material layer disposed on the substrate is determined. The flow rate of one or more processing components is then adjusted to affect the rate of removal of the material layer disposed on the substrate.

摘要翻译： 本文所述的实施例提供了一种用于抛光衬底表面的方法。 所述方法通常包括在处理期间将处理组件存储在多个存储单元中，并且将处理组件组合以在将处理组件流动到抛光垫的同时产生浆料。 使用浆料对基材进行研磨，并测定设置在基材上的材料层的厚度。 然后调整一个或多个处理部件的流速以影响设置在基板上的材料层的去除速率。

公开(公告)号：US20090061741A1

公开(公告)日：2009-03-05

申请号：US11849724

申请日：2007-09-04

申请人： Zhihong Wang ,  Alain Duboust ,  Wei-Yung Hsu ,  Yan Wang

发明人： Zhihong Wang ,  Alain Duboust ,  Wei-Yung Hsu ,  Yan Wang

IPC分类号： B24B7/04

CPC分类号： B24B37/042 ,  H01L21/67219

摘要： A method for processing a substrate having a conductive layer disposed thereon is provided. The substrate is coupled with a planarizing head. The planarizing head is moved to a position above a polishing pad assembly. The planarizing pad is positioned relative to the polishing pad assembly without applying a voltage to the substrate. A first voltage is applied to the substrate for a first time period. A second voltage is applied to the substrate for a second time period in order to remove a portion of the conductive layer, wherein the second voltage is greater than the first voltage. In certain embodiments, applying a first voltage to the substrate further comprises forming a uniform passivation layer on the conductive layer.

摘要翻译： 提供一种处理其上设置有导电层的基板的方法。 衬底与平坦化头结合。 平坦化头移动到抛光垫组件上方的位置。 平面化焊盘相对于抛光垫组件定位，而不向衬底施加电压。 第一次施加第一电压到基板。 向基板施加第二电压第二时间段，以便去除导电层的一部分，其中第二电压大于第一电压。 在某些实施例中，向衬底施加第一电压还包括在导电层上形成均匀的钝化层。

公开(公告)号：US20090036042A1

公开(公告)日：2009-02-05

申请号：US12239725

申请日：2008-09-26

申请人： Ho Seon Shin ,  Gary C. Ettinger ,  Donald J. K. Olgado ,  Erik C. Wasinger ,  Sen-Hou Ko ,  Charles I. Dodds ,  Yufei Chen ,  Wei-Yung Hsu

发明人： Ho Seon Shin ,  Gary C. Ettinger ,  Donald J. K. Olgado ,  Erik C. Wasinger ,  Sen-Hou Ko ,  Charles I. Dodds ,  Yufei Chen ,  Wei-Yung Hsu

IPC分类号： B24B5/00

CPC分类号： B24B9/065 ,  B24B21/002 ,  B24B41/067 ,  B24B49/16 ,  B24B57/02

摘要： Methods, systems and apparatus are provided for polishing an edge of a substrate. The invention includes an apparatus adapted to apply a preset pressure to a polishing film in contact with an edge of a substrate. The apparatus includes an actuator adapted to apply a preset pressure to the polishing film; and a controller coupled to the actuator and adapted to receive a signal indicative of a condition of the edge of the substrate, and to adjust a pressure applied by the actuator to the polishing film so as to maintain the preset pressure based on the received signal. Numerous other aspects are provided.

摘要翻译： 提供了用于抛光衬底边缘的方法，系统和装置。 本发明包括适于将预设压力施加到与衬底的边缘接触的抛光膜的装置。 该装置包括致动器，其适于对抛光膜施加预设压力; 以及控制器，其耦合到所述致动器并且适于接收指示所述基板的边缘的状态的信号，并且调整由所述致动器施加到所述抛光膜的压力，以便基于所接收的信号来保持所述预设压力。 提供了许多其他方面。