公开(公告)号：US11862458B2

公开(公告)日：2024-01-02

申请号：US17469529

申请日：2021-09-08

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. Citla ,  Soham Asrani ,  Joshua Rubnitz ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/02 ,  H01L21/3065 ,  H01J37/32 ,  H01L21/311

CPC classification number: H01L21/02274 ,  H01J37/32146 ,  H01L21/3065 ,  H01L21/31116 ,  H01J2237/332 ,  H01J2237/334

Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

公开(公告)号：US20230326925A1

公开(公告)日：2023-10-12

申请号：US17715331

申请日：2022-04-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Anthony Cockburn ,  Vanessa Pena ,  Daniel Philippe Cellier ,  John Tolle ,  Thomas Kirschenheiter ,  Wei Hong ,  Ellie Y. Yieh ,  Mehul Naik ,  Seshadri Ramaswami

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/0259 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/30604 ,  H01L21/823807 ,  H01L29/66742

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

公开(公告)号：US20230071366A1

公开(公告)日：2023-03-09

申请号：US17469529

申请日：2021-09-08

Applicant: Applied Materials, Inc.

Inventor： Bhargav S. Citla ,  Soham Asrani ,  Joshua Rubnitz ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/311 ,  H01J37/32

Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

公开(公告)号：US20220172948A1

公开(公告)日：2022-06-02

申请号：US17672305

申请日：2022-02-15

Applicant: Applied Materials, Inc.

Inventor： Jie Zhou ,  Erica Chen ,  Qiwei Liang ,  Chentsau Chris Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/26

Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.

公开(公告)号：US20210294216A1

公开(公告)日：2021-09-23

申请号：US16825393

申请日：2020-03-20

Applicant: Applied Materials, Inc.

Inventor： Huixiong Dai ,  Mangesh Ashok Bangar ,  Srinivas D. Nemani ,  Christopher S. Ngai ,  Ellie Y. Yieh

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/16 ,  G03F7/38 ,  G03F7/30

Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.

公开(公告)号：US10566226B2

公开(公告)日：2020-02-18

申请号：US14933651

申请日：2015-11-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Sriskantharajah Thirunavukarasu ,  Eng Sheng Peh ,  Srinivas D. Nemani ,  Arvind Sundarrajan ,  Avinash Avula ,  Ellie Y. Yieh ,  Michael Rice ,  Ginetto Addiego

IPC: B65D85/48 ,  H01L21/673 ,  B25J11/00

Abstract: Embodiments of multi-cassette carrying cases are provided herein. In some embodiments a multi-cassette carrying case includes: a body having an inner volume; a door coupled to the body to selectively seal off the inner volume; and a plurality of cassette holders disposed in the inner volume to hold one or more substrate cassettes. In some embodiments, a method of transferring substrates includes: placing a substrate in a substrate cassette, wherein an inner volume of the substrate cassette is sealed from an environment outside of the substrate cassette; and placing the substrate cassette in a multi-cassette carrying case.

公开(公告)号：US10566188B2

公开(公告)日：2020-02-18

申请号：US16035983

申请日：2018-07-16

Applicant: Applied Materials, Inc.

Inventor： Maximillian Clemons ,  Michel Ranjit Frei ,  Mahendra Pakala ,  Mehul B. Naik ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/00 ,  H01L21/02

Abstract: Embodiments of the present disclosure generally relate to a film treatment process. In one embodiment, a transition metal oxide layer including a dopant is deposited on a substrate. After the doped transition metal oxide layer is deposited, a high pressure annealing process is performed on the doped transition metal oxide layer to densify the doped transition metal oxide without outgassing of the dopant. The high pressure annealing process is performed in an ambient environment including the dopant and at a pressure greater than 1 bar.

公开(公告)号：US10347516B2

公开(公告)日：2019-07-09

申请号：US14933635

申请日：2015-11-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Sriskantharajah Thirunavukarasu ,  Eng Sheng Peh ,  Srinivas D. Nemani ,  Arvind Sundarrajan ,  Avinash Avula ,  Ellie Y. Yieh

IPC: H01L21/673 ,  H01L21/677 ,  H01L21/67

Abstract: Embodiments of substrate transfer chambers are provided herein. In some embodiments, a substrate transfer chamber includes a body having an interior volume, wherein a bottom portion of the body includes a first opening; an adapter plate coupled to the bottom portion of the body to couple the substrate transfer chamber to a load lock chamber of a substrate processing system; wherein the adapter plate includes a second opening aligned with the first opening to fluidly couple the interior volume with an inner volume of the load lock chamber; a cassette support disposed in the interior volume to support a substrate cassette; and a lift actuator coupled to the cassette support to lower or raise the substrate cassette into or out of the load lock chamber.

公开(公告)号：US10153187B2

公开(公告)日：2018-12-11

申请号：US14933628

申请日：2015-11-05

Applicant: APPLIED MATERIALS, INC.

Inventor： Sriskantharajah Thirunavukarasu ,  Eng Sheng Peh ,  Srinivas D. Nemani ,  Arvind Sundarrajan ,  Avinash Avula ,  Ellie Y. Yieh

IPC: H01L21/673 ,  H01L21/67

Abstract: Embodiments method and apparatus for transferring a substrate are provided herein. In some embodiments, a substrate cassette includes a body having an upper portion and a lower portion, the upper portion and the lower portion defining an interior volume when the upper portion is coupled to the lower portion; a locking mechanism moveable between a locked position, in which the upper and lower portions are coupled, and an unlocked position, in which the lower portion can be separated from the upper portion; and a load distribution plate coupled to an upper surface of the upper portion along an edge of the upper portion to distribute a load applied to the load distribution plate.

公开(公告)号：US20180025931A1

公开(公告)日：2018-01-25

申请号：US15217328

申请日：2016-07-22

Applicant: APPLIED MATERIALS, INC.

Inventor： Srinivas D. Nemani ,  Shambhu N. Roy ,  Gautam Pisharody ,  Douglas A. Buchberger, JR. ,  Ellie Y. Yieh ,  Zhong Qiang Hua

IPC: H01L21/683 ,  C23C16/513

CPC classification number: H01L21/6833 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/513

Abstract: A processed wafer is described that may be used as a workpiece carrier in semiconductor and mechanical processing. In some examples, the workpiece carrier includes a substrate, an electrode formed on the substrate to carry an electric charge to grip a workpiece, a through hole through the substrate and connected to the electrode, and a dielectric layer over the substrate to isolate the electrode from the workpiece.