公开(公告)号：US07018876B2

公开(公告)日：2006-03-28

申请号：US10871772

申请日：2004-06-18

申请人： Leo Mathew ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Ramachandran Muralidhar

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7887

摘要： A transistor (103) with a vertical structure (113) that includes a dielectric structure (201) below a semiconductor structure (109). The semiconductor structure includes a channel region (731) and source/drain regions (707, 709). The transistor includes a gate structure (705, 703) that has a portion laterally adjacent to the semiconductor structure and a portion laterally adjacent to the dielectric structure. In one embodiment, the gate structure is a floating gate structure wherein a control gate structure (719) also includes portion laterally adjacent to the dielectric structure and a portion laterally adjacent to the semiconductor structure. In some examples, having a portion of the floating gate and a portion of the control gate adjacent to the dielectric structure acts to increase the control gate to floating gate capacitance without significantly increasing the capacitance of the floating gate to channel region.

摘要翻译： 一种具有垂直结构（113）的晶体管（103），其包括半导体结构（109）下面的电介质结构（201）。 半导体结构包括沟道区（731）和源极/漏极区（707,709）。 晶体管包括具有与半导体结构横向相邻的部分和与电介质结构横向相邻的部分的栅极结构（705,703）。 在一个实施例中，栅极结构是浮动栅极结构，其中控制栅极结构（719）还包括横向邻近电介质结构的部分和与半导体结构横向相邻的部分。 在一些示例中，具有浮置栅极的一部分和与电介质结构相邻的控制栅极的一部分用于将控制栅极增加到浮置栅极电容，而不显着增加浮置栅极到沟道区的电容。

公开(公告)号：US06991984B2

公开(公告)日：2006-01-31

申请号：US10765804

申请日：2004-01-27

申请人： Paul A. Ingersoll ,  Gowrishankar L. Chindalore ,  Ramachandran Muralidhar

发明人： Paul A. Ingersoll ,  Gowrishankar L. Chindalore ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L29/42324 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/4925 ,  H01L29/4958

摘要： To increase the gate coupling ratio of a semiconductor device 10, discrete elements 22, such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements 22 are pre-formed in a vapor phase and are attached to the semiconductor device 10 by electrostatic force. In one embodiment, the discrete elements 22 are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer 17 may be formed between the floating gate 16 and the discrete elements 22.

摘要翻译： 为了增加半导体器件10的栅极耦合比，离散元件22（例如纳米晶体）沉积在浮动栅极16上。 在一个实施例中，分立元件22预先形成为气相并且通过静电力附着到半导体器件10。 在一个实施例中，分立元件22预先形成在不同于它们附接的腔室的腔室中。 在另一个实施例中，相同的室用于整个沉积工艺。 可选的界面层17可以形成在浮动栅极16和离散元件22之间。

公开(公告)号：US06903967B2

公开(公告)日：2005-06-07

申请号：US10443908

申请日：2003-05-22

申请人： Leo Mathew ,  Robert F. Steimle ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Robert F. Steimle ,  Ramachandran Muralidhar

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC分类号： B82Y10/00 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7887 ,  H01L29/7923

摘要： A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.

摘要翻译： 一种存储器，其具有邻近半导体结构的相对侧壁的栅极结构，该半导体结构包括沟道区和栅极结构与相对侧壁之间的多个电荷存储位置。 沟道区域位于两个电流端子区域之间，在一个示例中，该区域用作源极/漏极区域。 存储器单元可以在存储单元的阵列中实现，其中一个栅极结构耦合到一个字线，而另一个栅极结构耦合到另一个字线。 在一个示例中，每个单元包括四个电荷存储位置，每个用于存储一位数据。

公开(公告)号：US20050057964A1

公开(公告)日：2005-03-17

申请号：US10443908

申请日：2003-05-22

申请人： Leo Mathew ,  Robert Steimle ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Robert Steimle ,  Ramachandran Muralidhar

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC分类号： B82Y10/00 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L29/66818 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7887 ,  H01L29/7923

摘要： A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example serve as the source/drain regions. A memory cell can be implemented in an array of memory cells wherein one gate structure is coupled to one word line and the other gate structure is coupled to another word line. In one example, each cell includes four charge storage locations, each for storing one bit of data.

摘要翻译： 一种存储器，其具有邻近半导体结构的相对侧壁的栅极结构，该半导体结构包括沟道区和栅极结构与相对侧壁之间的多个电荷存储位置。 沟道区域位于两个电流端子区域之间，在一个示例中，该区域用作源极/漏极区域。 存储器单元可以在存储单元的阵列中实现，其中一个栅极结构耦合到一个字线，而另一个栅极结构耦合到另一个字线。 在一个示例中，每个单元包括四个电荷存储位置，每个用于存储一位数据。

公开(公告)号：US06297095B1

公开(公告)日：2001-10-02

申请号：US09596399

申请日：2000-06-16

申请人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

发明人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

IPC分类号： H01L21336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/66439 ,  H01L29/7888

摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).

摘要翻译： 提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。 该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。 然后在隧道介电层（14）上生长多个纳米团簇（19）。 在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。 为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。 然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。 在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间 电极（24）。

公开(公告)号：US08895384B2

公开(公告)日：2014-11-25

申请号：US13293210

申请日：2011-11-10

申请人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

发明人： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364

摘要： A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.

摘要翻译： 提供了具有通道材料的金属栅极结构及其制造方法。 该方法包括在衬底上形成虚拟栅极结构。 该方法还包括在虚拟栅极结构的侧壁上形成侧壁结构。 该方法还包括去除伪栅极结构以形成由侧壁结构限定的第一沟槽和第二沟槽。 该方法还包括在第一沟槽和第二沟槽中的衬底上形成沟道材料。 该方法还包括在第一沟槽被掩蔽的同时从第二沟槽去除沟道材料。 该方法还包括用栅极材料填充第一沟槽和第二沟槽的剩余部分。

公开(公告)号：US08541814B2

公开(公告)日：2013-09-24

申请号：US13084594

申请日：2011-04-12

申请人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J Oldiges ,  Viorel Ontalus

发明人： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J Oldiges ,  Viorel Ontalus

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84

摘要： A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

公开(公告)号：US20110269276A1

公开(公告)日：2011-11-03

申请号：US12770792

申请日：2010-04-30

申请人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

发明人： Unoh Kwon ,  Dechao Guo ,  Siddarth A. Krishnan ,  Ramachandran Muralidhar

IPC分类号： H01L21/8238 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/1054 ,  H01L29/42372 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843

摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.

摘要翻译： 在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。 使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构 。 使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属 层。

公开(公告)号：US20090184309A1

公开(公告)日：2009-07-23

申请号：US12016733

申请日：2008-01-18

申请人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

发明人： Leo Mathew ,  Dharmesh Jawarani ,  Tushar P. Merchant ,  Ramachandran Muralidhar

IPC分类号： H01L45/00

CPC分类号： H01L45/1675 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/126 ,  H01L45/144

摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.

摘要翻译： 形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。 形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。 当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。 当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

公开(公告)号：US07364969B2

公开(公告)日：2008-04-29

申请号：US11172728

申请日：2005-07-01

申请人： Erwin J. Prinz ,  Ramachandran Muralidhar

发明人： Erwin J. Prinz ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/823857 ,  Y10S438/962

摘要： A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

摘要翻译： 半导体制造工艺包括在覆盖衬底的第一区域的隧道氧化物上形成多晶硅纳米晶体。 沉积第二电介质覆盖在第一区域和第二区域上。 在不提供覆盖第一区域中的第二电介质的任何保护层的情况下，进行额外的热氧化步骤而不氧化纳米晶体。 然后将栅极电极膜沉积在第二电介质上并被图案化以形成第一和第二栅电极。 第二电介质可以是退火的CVD氧化物。 额外的热氧化可以包括通过干式氧化形成覆盖在半导体衬底的第三区域上的第三电介质。 干燥氧化在第二区域中产生第二电介质下面的界面氧化硅。 然后可以暴露基板的第四区域的上表面，并在第四区域的上表面上形成第四电介质。