公开(公告)号：US06297095B1

公开(公告)日：2001-10-02

申请号：US09596399

申请日：2000-06-16

申请人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

发明人： Ramachandran Muralidhar ,  Chitra K. Subramanian ,  Sucharita Madhukar ,  Bruce E. White ,  Michael A. Sadd ,  Sufi Zafar ,  David L. O'Meara ,  Bich-Yen Nguyen

IPC分类号： H01L21336

CPC分类号： H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/66439 ,  H01L29/7888

摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).

摘要翻译： 提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。 该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。 然后在隧道介电层（14）上生长多个纳米团簇（19）。 在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。 为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。 然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。 在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间 电极（24）。

公开(公告)号：US06413819B1

公开(公告)日：2002-07-02

申请号：US09595821

申请日：2000-06-16

申请人： Sufi Zafar ,  Ramachandran Muralidhar ,  Bich-Yen Nguyen ,  Sucharita Madhukar ,  Daniel T. Pham ,  Michael A. Sadd ,  Chitra K. Subramanian

发明人： Sufi Zafar ,  Ramachandran Muralidhar ,  Bich-Yen Nguyen ,  Sucharita Madhukar ,  Daniel T. Pham ,  Michael A. Sadd ,  Chitra K. Subramanian

IPC分类号： H01L21336

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/7883 ,  H01L29/7888

摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).

摘要翻译： 提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。 该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。 然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。 该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。 一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。 在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。 然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。 然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

公开(公告)号：US07235440B2

公开(公告)日：2007-06-26

申请号：US10630969

申请日：2003-07-31

申请人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

发明人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

IPC分类号： H01L21/8242

CPC分类号： H01L21/28194 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.

摘要翻译： 使用低压处理形成超薄氧化层，以实现衬底的自限制氧化并提供超薄氧化物。 待处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层，氮化物层，高k层，或者可以缺少初始介电层。 处理可以使用间歇式处理室进行，或者使用单晶圆处理室进行。 本发明的一个实施例提供了Si衬底的自限制氧化，其导致厚度为约15A的SiO 2层，其中SiO 2层的厚度 在基材上变化小于约1A。

公开(公告)号：US06974779B2

公开(公告)日：2005-12-13

申请号：US10662875

申请日：2003-09-16

申请人： David L O'Meara ,  Cory Wajda ,  Tsuyoshi Takahashi ,  Alessandro Callegari ,  Kristen Scheer ,  Sufi Zafar ,  Paul Jamison

发明人： David L O'Meara ,  Cory Wajda ,  Tsuyoshi Takahashi ,  Alessandro Callegari ,  Kristen Scheer ,  Sufi Zafar ,  Paul Jamison

IPC分类号： H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/02181 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31658 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method is provided for forming a microstructure with an interfacial oxide layer by using a diffusion filter layer to control the oxidation properties of a substrate associated with formation of a high-k layer into the microstructure. The diffusion filter layer controls the oxidation of the surface. The interfacial oxide layer can be formed during an oxidation process that is carried out following deposition of a high-k layer onto the diffusion filter layer, or during deposition of a high-k layer onto the diffusion filter layer.

公开(公告)号：US07202186B2

公开(公告)日：2007-04-10

申请号：US10630970

申请日：2003-07-31

申请人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

发明人： David L O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  C23C16/308 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L21/67098 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

摘要翻译： 使用低压处理形成超薄氧氮化物层，以实现衬底的自限制氧化并提供超薄氧氮化物。 要处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层或氮化物层，或者可以缺少初始介电层。 处理可以使用间歇式处理室或单晶片处理室进行。

公开(公告)号：US08409867B2

公开(公告)日：2013-04-02

申请号：US13232395

申请日：2011-09-14

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01N15/06 ,  G01N33/00 ,  G01N33/48

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20130005156A1

公开(公告)日：2013-01-03

申请号：US13602118

申请日：2012-09-01

申请人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

发明人： Hemanth Jagannathan ,  Takashi Ando ,  Lisa F. Edge ,  Sufi Zafar ,  Changhwan Choi ,  Paul C. Jamison ,  Vamsi K. Paruchuri ,  Vijay Narayanan

IPC分类号： H01L21/324

CPC分类号： H01L29/42364 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

摘要： Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

公开(公告)号：US20120001614A1

公开(公告)日：2012-01-05

申请号：US13232395

申请日：2011-09-14

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01R1/30 ,  G01N27/00

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US08052931B2

公开(公告)日：2011-11-08

申请号：US12651504

申请日：2010-01-04

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01N15/06 ,  G01N33/00

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20110163812A1

公开(公告)日：2011-07-07

申请号：US12651504

申请日：2010-01-04

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： H03F3/16

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。