公开(公告)号：US08299535B2

公开(公告)日：2012-10-30

申请号：US12823163

申请日：2010-06-25

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

公开(公告)号：US08278197B2

公开(公告)日：2012-10-02

申请号：US12130460

申请日：2008-05-30

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Jeffrey B. Johnson ,  Chung H. Lam ,  Beth A. Rainey ,  Michael J. Zierak

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Jeffrey B. Johnson ,  Chung H. Lam ,  Beth A. Rainey ,  Michael J. Zierak

IPC分类号： H01L21/265

CPC分类号： H01L29/66477 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7834 ,  H01L29/792

摘要： The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

摘要翻译： 本发明提供了一种通过改变扩展和光晕注入来提高快速移位设备的可编程性的方法，其将编程时间缩短到几毫秒，而不是从设备的一侧简单地省略它 现有技术中的瞬时移位装置。 本发明包括其中不使用附加掩模的实施例，或者采用一个附加掩模。 与常规的延伸植入过程相比，改变的延伸植入物以降低的离子剂量进行，而改变的晕轮植入物以比常规的晕轮植入物更高的离子剂量进行。 改变的光晕/延伸注入将电场的峰值移动到延伸电介质间隔物下方。

公开(公告)号：US20120199907A1

公开(公告)日：2012-08-09

申请号：US13449419

申请日：2012-04-18

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L27/12 ,  G06F17/50

CPC分类号： H01L29/93 ,  H01L29/7391

摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.

摘要翻译： 变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。 具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。 在第二掺杂半导体区域和第二电极之间形成超破坏结。 栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。 还提供了变容二极管的设计结构。

公开(公告)号：US08236632B2

公开(公告)日：2012-08-07

申请号：US12899635

申请日：2010-10-07

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

摘要翻译： 半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入 在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。 在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。 在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。 在其他示例性实施例中，没有接合对接。 在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

公开(公告)号：US20120187490A1

公开(公告)日：2012-07-26

申请号：US13426547

申请日：2012-03-21

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

公开(公告)号：US20120119302A1

公开(公告)日：2012-05-17

申请号：US12944018

申请日：2010-11-11

申请人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

发明人： Chengwen Pei ,  Jeffrey B. Johnson ,  Zhengwen Li ,  Jian Yu

IPC分类号： H01L23/532 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L21/76879 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76805 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

摘要翻译： 提供一种电结构，其包括存在于半导体衬底上的电介质层和通过电介质层存在的通路开口。 在通孔开口内存在互连。 在半导体衬底中存在金属半导体合金接触。 金属半导体合金触点具有由相对于通孔开口的中心线的凸曲面限定的周长。 限定金属半导体合金触点的凸曲率的端点与通孔开口的侧壁，互连的侧壁和半导体衬底的上表面之间的界面对准。

公开(公告)号：US20110316044A1

公开(公告)日：2011-12-29

申请号：US12823163

申请日：2010-06-25

申请人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

发明人： Kevin K. Chan ,  Abhishek Dube ,  Judson R. Holt ,  Jeffrey B. Johnson ,  Jinghong Li ,  Dae-Gyu Park ,  Zhengmao Zhu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7834 ,  H01L29/7848

摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.

摘要翻译： 公开了在其中具有嵌入的应力元件的半导体结构。 所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。 所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。 器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。 该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。 每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层 位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。 该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

公开(公告)号：US08039875B2

公开(公告)日：2011-10-18

申请号：US11850776

申请日：2007-09-06

申请人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

发明人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC分类号： H01L27/148 ,  H01L31/062

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281 ,  H01L31/1037

摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

摘要翻译： 本发明涉及一种像素传感器单元的设计结构。 像素传感器单元对于给定的光量大约使可用信号加倍。 具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上​​，以及p型收集阱区域 用于收集由撞击光子产生的孔的基板的表面。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

公开(公告)号：US07698112B2

公开(公告)日：2010-04-13

申请号：US11294550

申请日：2005-12-06

申请人： Stephen E. Fischer ,  Jeffrey B. Johnson ,  Ralph W. Young

发明人： Stephen E. Fischer ,  Jeffrey B. Johnson ,  Ralph W. Young

IPC分类号： G06F7/50 ,  G06F17/50 ,  G06F9/45 ,  G06G7/48

CPC分类号： G06T17/20

摘要： A dynamic directory and tetrahedralization method. The dynamic directory of degree of freedom data for elements in a non-conformal mixed-element mesh includes elements subdividable into tetrahedral, in which a respective degree of freedom value is stored for each element, wherein the degree of freedom value is current as element subdivision proceeds. The tetrahedralization method includes providing a non-conformal mixed element mesh comprising elements subdividable into tetrahedra, identifying respective degree of freedom values for the elements in the mesh, and performing element subdivision based on the degree of freedom values of elements in the mesh.

摘要翻译： 动态目录和四面体化方法。 非共形混合元素网格中的元素的自由度数据的动态目录包括可细分为四面体的元素，其中为每个元素存储相应的自由度值，其中自由度值作为元素细分 收益。 四面体化方法包括提供包括可细分成四面体的元素的非共形混合元素网格，识别网格中元素的相应自由度值，以及基于网格中的元素的自由度值执行元素细分。

公开(公告)号：US07563636B2

公开(公告)日：2009-07-21

申请号：US12172304

申请日：2008-07-14

申请人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

发明人： James W. Adkisson ,  Andres Bryant ,  John J. Ellis-Monaghan ,  Mark D. Jaffe ,  Jeffrey B. Johnson ,  Alain Loiseau

IPC分类号： H01L21/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

摘要翻译： 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。