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    FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE
    1.
    发明申请
    FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE 有权
    具有TRENCH植入的FET结构以提高反向通道泄漏和体电阻

    公开(公告)号：US20120086077A1

    公开(公告)日：2012-04-12

    申请号：US12899635

    申请日：2010-10-07

    申请人： DAVID M FRIED ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    发明人： DAVID M FRIED ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L29/06 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

    摘要翻译： 半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入 在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。 在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。 在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。 在其他示例性实施例中，没有接合对接。 在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

    FET structures with trench implantation to improve back channel leakage and body resistance
    2.
    发明授权
    FET structures with trench implantation to improve back channel leakage and body resistance 有权
    具有沟槽注入的FET结构，以改善背沟道泄漏和体电阻

    公开(公告)号：US08236632B2

    公开(公告)日：2012-08-07

    申请号：US12899635

    申请日：2010-10-07

    申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/338

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

    摘要翻译： 半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入 在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。 在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。 在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。 在其他示例性实施例中，没有接合对接。 在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

    FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE
    3.
    发明申请
    FET STRUCTURES WITH TRENCH IMPLANTATION TO IMPROVE BACK CHANNEL LEAKAGE AND BODY RESISTANCE 有权
    具有TRENCH植入的FET结构以提高反向通道泄漏和体电阻

    公开(公告)号：US20120187490A1

    公开(公告)日：2012-07-26

    申请号：US13426547

    申请日：2012-03-21

    申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

    摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

    FET structures with trench implantation to improve back channel leakage and body resistance
    4.
    发明授权
    FET structures with trench implantation to improve back channel leakage and body resistance 有权
    具有沟槽注入的FET结构，以改善背沟道泄漏和体电阻

    公开(公告)号：US08809953B2

    公开(公告)日：2014-08-19

    申请号：US13426547

    申请日：2012-03-21

    申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

    摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

    摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

    DEEP TRENCH HEAT SINK
    6.
    发明申请
    DEEP TRENCH HEAT SINK 审中-公开
    深层烫金加热

    公开(公告)号：US20140008756A1

    公开(公告)日：2014-01-09

    申请号：US13543966

    申请日：2012-07-09

    申请人： Chengwen Pei ,  Gan Wang

    发明人： Chengwen Pei ,  Gan Wang

    IPC分类号： H01L21/306 ,  H01L23/34

    CPC分类号： H01L23/3677 ,  H01L21/84 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method including providing a silicon-on-insulator (SOI) substrate including a SOI layer, a buried oxide layer, and a base layer; the buried oxide layer is located below the SOI layer and above the base layer, and the buried oxide layer insulates the SOI layer from the base layer; etching a deep trench into the SOI substrate, the deep trench having a sidewall and a bottom, the deep trench extends from a top surface of the SOI layer, through the buried oxide layer, down to a location within the base layer; forming a dielectric liner on the sidewall and the bottom of the deep trench; forming a conductive fill material on top of the dielectric liner and substantially filling the deep trench, the fill material being thermally conductive; and transferring heat from the SOI layer to the base layer via the fill material.

    摘要翻译： 一种包括提供包括SOI层，掩埋氧化物层和基底层的绝缘体上硅（SOI）衬底的方法; 掩埋氧化物层位于SOI层的下方并且在基底层之上，并且掩埋氧化层使SOI层与基底层绝缘; 将深沟槽蚀刻到SOI衬底中，深沟槽具有侧壁和底部，深沟槽从SOI层的顶表面延伸穿过掩埋氧化物层到底层内的位置; 在所述深沟槽的侧壁和底部上形成介电衬垫; 在电介质衬垫的顶部上形成导电填充材料并基本上填充深沟槽，填充材料是导热的; 并且通过填充材料将热量从SOI层传递到基底层。