公开(公告)号：US08803248B2

公开(公告)日：2014-08-12

申请号：US13241324

申请日：2011-09-23

申请人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

发明人： Sang-Jine Park ,  Bo-Un Yoon ,  Jeong-Nam Han ,  Myung-Geun Song

IPC分类号： H01L27/088

CPC分类号： H01L29/66636 ,  H01L21/28518 ,  H01L21/76802 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

摘要： Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

摘要翻译： 提供一种可以促进自对准硅化物工艺并且可以防止栅极由于不对准而被损坏的半导体器件，以及半导体器件的制造方法。 该方法包括在具有形成在栅极图案的两侧的栅极图案和源极/漏极区域的衬底上形成第一绝缘层图案，第一绝缘层图案具有源极/漏极区域的暴露部分，形成硅化物 在所述暴露的源极/漏极区上形成第二绝缘层，以在所述衬底的整个表面上形成覆盖所述第一绝缘层图案和所述硅化物层的第二绝缘层，以及在所述第二绝缘层中形成接触孔以露出所述硅化物层。

公开(公告)号：US08735250B2

公开(公告)日：2014-05-27

申请号：US13241957

申请日：2011-09-23

申请人： Jong-Won Lee ,  Bo-Un Yoon ,  Seung-Jae Lee

发明人： Jong-Won Lee ,  Bo-Un Yoon ,  Seung-Jae Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/28008 ,  H01L21/28105 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545

摘要： Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

摘要翻译： 提供了形成半导体器件的栅极的方法。 所述方法可以包括在具有第一导电类型的第一衬底区域中形成第一凹槽，并在具有第二导电类型的第二衬底区域中形成第二凹部。 所述方法还可以包括在第一和第二凹部中形成高k层。 所述方法还可以包括在第一和第二衬底区域中的高k层上提供第一金属，第一金属设置在第二凹槽内。 所述方法还可以包括从第二凹部移除第一金属的至少一部分，同时保护第一凹槽内的材料不被去除。 所述方法还可以包括在从第二凹部去除第一金属的至少一部分之后，在第二凹部内提供第二金属。

公开(公告)号：US08709942B2

公开(公告)日：2014-04-29

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il-Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US20130023119A1

公开(公告)日：2013-01-24

申请号：US13488478

申请日：2012-06-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Doo-Sung Yun ,  Bo-Un Yoon ,  Il- Young Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/768

CPC分类号： H01L21/76808 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816

摘要： In a method for fabricating a semiconductor device, a substrate is provided including an interlayer dielectric layer and first and second hard mask patterns sequentially stacked thereon. A first trench is provided in the interlayer dielectric layer through the second hard mask pattern and the first hard mask pattern. A filler material is provided on the interlayer dielectric layer and the second hard mask pattern to fill the first trench. An upper portion of the second hard mask pattern is exposed by partially removing the filler material. The second hard mask pattern is removed, and remaining filler material is removed from the first trench. A wiring is formed by filling the first trench with a conductive material.

摘要翻译： 在制造半导体器件的方法中，提供了包括层间介电层和顺序堆叠在其上的第一和第二硬掩模图案的衬底。 第一沟槽通过第二硬掩模图案和第一硬掩模图案设置在层间介质层中。 在层间介电层和第二硬掩模图案上设置填充材料以填充第一沟槽。 通过部分去除填充材料来暴露第二硬掩模图案的上部。 去除第二硬掩模图案，并且从第一沟槽去除剩余的填充材料。 通过用导电材料填充第一沟槽来形成布线。

公开(公告)号：US20120088358A1

公开(公告)日：2012-04-12

申请号：US13241957

申请日：2011-09-23

申请人： Jong-Won Lee ,  Bo-Un Yoon ,  Seung-Jae Lee

发明人： Jong-Won Lee ,  Bo-Un Yoon ,  Seung-Jae Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28008 ,  H01L21/28105 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/513 ,  H01L29/66545

摘要： Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.

摘要翻译： 提供了形成半导体器件的栅极的方法。 所述方法可以包括在具有第一导电类型的第一衬底区域中形成第一凹槽，并在具有第二导电类型的第二衬底区域中形成第二凹部。 所述方法还可以包括在第一和第二凹部中形成高k层。 所述方法还可以包括在第一和第二衬底区域中的高k层上提供第一金属，第一金属设置在第二凹槽内。 所述方法还可以包括从第二凹部移除第一金属的至少一部分，同时保护第一凹槽内的材料不被去除。 所述方法还可以包括在从第二凹部去除第一金属的至少一部分之后，在第二凹部内提供第二金属。

公开(公告)号：US20120052682A1

公开(公告)日：2012-03-01

申请号：US13204862

申请日：2011-08-08

申请人： Sang-Kyun Kim ,  Jong-Won Lee ,  Eui-Hoon Jung ,  Bo-Un Yoon ,  Sang-Hyun Park ,  Seung-Jae Lee ,  Yun-Jeong Kim

发明人： Sang-Kyun Kim ,  Jong-Won Lee ,  Eui-Hoon Jung ,  Bo-Un Yoon ,  Sang-Hyun Park ,  Seung-Jae Lee ,  Yun-Jeong Kim

IPC分类号： H01L21/302 ,  C09K13/00

CPC分类号： H01L21/3212 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463

摘要： A polishing slurry for polishing an aluminum film includes an abrasive agent, an oxidizing agent, an anti-corrosion agent, and a removal rate reducing agent that is an anionic compound exhibiting a negative charge in the slurry. The polishing slurry can be used in a method of manufacturing a semiconductor device.

摘要翻译： 用于抛光铝膜的抛光浆料包括研磨剂，氧化剂，防腐蚀剂和作为在浆料中显示负电荷的阴离子化合物的去除速率还原剂。 抛光浆料可用于制造半导体器件的方法中。

公开(公告)号：US20110306197A1

公开(公告)日：2011-12-15

申请号：US13156729

申请日：2011-06-09

申请人： Young-Hoo Kim ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park

发明人： Young-Hoo Kim ,  Bo-Un Yoon ,  Kun-Tack Lee ,  Dae-Hyuk Kang ,  Im-Soo Park

IPC分类号： H01L21/3205

CPC分类号： H01L28/82

摘要： Method of manufacturing semiconductor device are provided including forming an insulation layer having a pad on a substrate; forming an etch stop layer on the insulation layer and the pad; forming a mold structure having at least one mold layer on the etch stop layer; forming a first supporting layer on the mold structure; etching the first supporting layer and the mold structure to form a first opening exposing the etch stop layer; forming a spacer on a sidewall of the first opening; etching the etch stop layer using the spacer as an etching mask to form a second opening, different from the first opening, exposing a first portion of the pad having a first associated area; etching the etch stop layer using the spacer as an etching mask to form a third opening exposing a second portion of the pad having a second associated area, the second associated area being larger than the first associated area; and etching the mold structure to form a fourth opening having a width larger than a width of the third opening.

摘要翻译： 提供制造半导体器件的方法，包括在衬底上形成具有衬垫的绝缘层; 在所述绝缘层和所述焊盘上形成蚀刻停止层; 形成在所述蚀刻停止层上具有至少一个模制层的模具结构; 在模具结构上形成第一支撑层; 蚀刻第一支撑层和模具结构以形成暴露蚀刻停止层的第一开口; 在所述第一开口的侧壁上形成间隔件; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成不同于所述第一开口的第二开口，暴露所述焊盘的具有第一相关区域的第一部分; 使用所述间隔物作为蚀刻掩模来蚀刻所述蚀刻停止层，以形成暴露所述焊盘的具有第二相关区域的第二部分的第三开口，所述第二相关区域大于所述第一相关区域; 并且蚀刻所述模具结构以形成宽度大于所述第三开口的宽度的第四开口。

公开(公告)号：US20110287625A1

公开(公告)日：2011-11-24

申请号：US13079202

申请日：2011-04-04

申请人： Dae-Hyuk Kang ,  Kun-Tack Lee ,  Dae-Hong Eom ,  Bo-Un Yoon ,  Jeong-Nam Han

发明人： Dae-Hyuk Kang ,  Kun-Tack Lee ,  Dae-Hong Eom ,  Bo-Un Yoon ,  Jeong-Nam Han

IPC分类号： H01L21/336

CPC分类号： H01L21/28123 ,  H01L21/3081 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/11524 ,  H01L29/40114

摘要： A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask.

摘要翻译： 在半导体器件中形成图案的方法包括在基板上形成蚀刻对象层，蚀刻对象层是基本上不含杂质的氧化物。 在蚀刻对象层上形成掩模，掩模是包含杂质的氧化物。 使用掩模将蚀刻对象层图案化为蚀刻掩模，然后去除掩模。 使用具有对基本上不含杂质的氧化物的蚀刻选择性的蚀刻剂去除掩模，以及在除去掩模期间包括杂质的氧化物，以限制在去除掩模期间对图案化的蚀刻对象层的损伤。

公开(公告)号：US20050145602A1

公开(公告)日：2005-07-07

申请号：US11055505

申请日：2005-02-10

申请人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

发明人： Jeong-Heon Park ,  Bo-Un Yoon ,  Jae-Dong Lee

IPC分类号： H01L21/66 ,  C03C25/68 ,  C23F1/00 ,  G01R31/26 ,  H01L21/4763 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L22/32 ,  H01L22/34

摘要： A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

公开(公告)号：US10128236B2

公开(公告)日：2018-11-13

申请号：US15007882

申请日：2016-01-27

申请人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

发明人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC分类号： H01L29/772 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

摘要： A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.