公开(公告)号：US20210066133A1

公开(公告)日：2021-03-04

申请号：US16988892

申请日：2020-08-10

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI

IPC: H01L21/8234 ,  H01L21/762

Abstract: A method is provided for producing a component based on a plurality of transistors on a substrate including an active area and an electrical isolation area, each transistor including a gate and spacers on either side of the gate, the electrical isolation area including at least one cavity formed as a hollow between a spacer of a first transistor of the plurality of transistors and a spacer of a second transistor of the plurality of transistors, the first and the second transistors being adjacent, the method including: forming the gates of the transistors; forming the spacers; and forming a mechanically constraining layer for the transistors; and after forming the spacers and before forming the mechanically constraining layer, forming a filling configured to at least partially fill, with a filling material, the at least one cavity within the electrical isolation area, between the spacers of the first and the second transistors.

公开(公告)号：US20210005443A1

公开(公告)日：2021-01-07

申请号：US16914541

申请日：2020-06-29

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Loic GABEN ,  Cyrille LE ROYER ,  Fabrice NEMOUCHI ,  Nicolas POSSEME ,  Shay REBOH

IPC: H01L21/02 ,  H01L21/8238 ,  H01L21/3105

Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strained semiconductor portion includes SiGe.

公开(公告)号：US20200335343A1

公开(公告)日：2020-10-22

申请号：US16919886

申请日：2020-07-02

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Lamia NOURI ,  Stefan LANDIS ,  Nicolas POSSEME

IPC: H01L21/266 ,  H01L31/18 ,  H01L21/265 ,  H01L21/308 ,  B81C1/00 ,  H01L21/306 ,  H01L21/3065

Abstract: A method for forming reliefs on a face of a substrate is provided, successively including forming a protective screen for protecting at least a first zone of the face; an implanting to introduce at least one species comprising carbon into the substrate from the face of the substrate, the forming of the protective screen and the implanting being configured to form, in the substrate, at least one carbon modified layer having a concentration of implanted carbon greater than or equal to an etching threshold only from a second zone of the face of the substrate not protected by the protective screen; removing the protective screen; and etching the substrate from the first zone selectively with respect to the second zone.

公开(公告)号：US20200211906A1

公开(公告)日：2020-07-02

申请号：US16712158

申请日：2019-12-12

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Cyrille LE ROYER

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092

Abstract: A method is provided for producing a microelectronic component on a substrate including in an exposed manner on a first face thereof, an active zone and an electrical isolation zone adjacent thereto, the method including forming a gate on the active zone, forming spacers each configured to cover a surface of a different edge of the gate, and forming source and drain zones by doping portions of the active zone adjacent to the gate, the method successively including forming a first layer of spacer material above the active zone and the electrical isolation zone; an ion implantation to produce doping of the portions through the first layer; removing a modified portion of the first layer disposed overlooking the portions, the modified portion coming from the ion implantation, the removing being configured to preserve at least part of the first layer at a level of edges of the gate.

公开(公告)号：US20200090941A1

公开(公告)日：2020-03-19

申请号：US16616275

申请日：2018-05-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Lamia NOURI ,  Frederic-Xavier GAI LIARD ,  Stefan LANDIS ,  Nicolas POSSEME

IPC: H01L21/3063 ,  H01L21/266 ,  H01L21/265 ,  H01L21/306

Abstract: A method for producing at least one pattern in a substrate is provided, including providing a substrate having a front face surmounted by at least one masking layer carrying at least one mask pattern, carrying out an ion implantation of the substrate so as to form at least one first zone having a resistivity ρ1 less than a resistivity ρ2 of at least one second non-modified zone, after the ion implantation step, immersing the substrate in an electrolyte, and removing the at least one first zone selectively at the at least one second zone, the removing including at least an application of an electrochemistry step to the substrate to cause a porosification of the at least one first zone selectively at the at least one second zone.

公开(公告)号：US20190278170A1

公开(公告)日：2019-09-12

申请号：US16304897

申请日：2017-05-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Raluca TIRON ,  Nicolas POSSEME ,  Xavier CHEVALIER ,  Christophe NAVARRO

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/311

Abstract: A method for the directed self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern, the guide pattern having a cavity with a bottom and side walls; forming a functionalisation layer on the guide pattern that has a first portion and a second portion disposed, respectively, on the bottom and side walls of the cavity; forming a protective layer on the first and second portions of the functionalisation layer; etching the protective layer and the second portion of the functionalisation layer such that a portion of the protective layer is retained and the side walls of the cavity are exposed, the retained portion of the protective layer having a thickness of less than 15 nm; selectively etching the portion of the protective layer relative to the first portion of the functionalisation layer and to the guide pattern; and depositing a block copolymer in the cavity.

公开(公告)号：US20180315614A1

公开(公告)日：2018-11-01

申请号：US15961338

申请日：2018-04-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME

IPC: H01L21/311 ,  H01L21/3115 ,  H01L21/8238

CPC classification number: H01L21/31116 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684

Abstract: A microelectronic method for etching a layer containing silicon nitride is provided, including the following successive steps: modifying the layer containing silicon nitride (SiN) so as to form at least one modified zone, the modifying including at least one implantation of ions made from hydrogen (H) in the layer containing SiN; and removing the at least one modified zone, the removing of the at least one modified zone including at least one step of etching of the at least one modified zone using a chemistry including at least: at least one compound chosen from the fluorocarbon compounds (CxFz) and the hydrofluorocarbon compounds (CxHyFz), and at least one compound chosen from SiwCl(2w+2) and SiwF(2w+2).

公开(公告)号：US20180286697A1

公开(公告)日：2018-10-04

申请号：US15759123

申请日：2016-09-09

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Aurélien SARRAZIN

IPC: H01L21/311 ,  H01L21/02 ,  G03F7/00

Abstract: A method for etching an assembled block copolymer layer including first and second polymer phases, in which the etching method includes exposing the assembled block copolymer layer to a plasma so as to etch the first polymer phase and simultaneously to deposit a carbon layer on the second polymer phase, wherein the plasma is formed from a gas mixture including a depolymerising gas and an etching gas selected among the hydrocarbons.

公开(公告)号：US20170345655A1

公开(公告)日：2017-11-30

申请号：US15606626

申请日：2017-05-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas POSSEME ,  Stefan LANDIS ,  Lamia NOURI

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L21/02694 ,  G02B3/0012 ,  G03F7/0005 ,  H01L21/02304 ,  H01L21/033 ,  H01L21/30608 ,  H01L21/3083 ,  H01L21/3213

Abstract: A method for producing patterns in a layer to be etched, from a stack including at least the layer to be etched and a masking layer overlying the layer to be etched, with the masking layer having at least one pattern. The method includes modifying a first area of the layer to be etched by ion implantation through the masking layer; depositing a buffer layer to cover the pattern of the masking layer; modifying another area of the layer to be etched, different from the first area, by ion implantation through the buffer layer, to a depth of the layer to be etched greater than the implantation depth of the preceding step of modifying; removing the buffer layer; removing the masking layer; removing the modified areas by etching them selectively to the non-modified areas of the layer to be etched.

公开(公告)号：US20170338157A1

公开(公告)日：2017-11-23

申请号：US15599663

申请日：2017-05-19

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Nicolas POSSEME ,  Laurent GRENOUILLET

IPC: H01L21/8238 ,  H01L21/32 ,  H01L21/3115 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/32 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78696

Abstract: A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing at least one first protective layer on the first and the second gate patterns; depositing, on the first and the second gate patterns, at least a first protective layer and a second protective layer overlying, the first protective layer, the second protective layer being made from a different material than that of the first protective layer; masking the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.