公开(公告)号：US20090087544A1

公开(公告)日：2009-04-02

申请号：US12039744

申请日：2008-02-29

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: B05D5/12

CPC classification number: H01L29/7923 ,  H01L27/115 ,  H01L27/11568

Abstract: The memory cell of the present invention has two independent storage regions embedded into two opposite sidewalls of the control gate respectively. In this way, the data storage can be more reliable. Other features of the present invention are that the thickness of the dielectric layers is different, and the two independent storage regions are formed on opposite bottom sides of the opening by the etching process and form a shape like a spacer. The advantage of the aforementioned method is that the fabricating process is simplified and the difficulty of self-alignment is reduced.

Abstract translation: 本发明的存储单元具有分别嵌入控制门的两个相对的侧壁中的两个独立的存储区域。 以这种方式，数据存储可以更可靠。 本发明的其他特征是电介质层的厚度不同，并且两个独立的存储区域通过蚀刻工艺形成在开口的相对的底侧上并形成像间隔物的形状。 上述方法的优点是简化了制造工艺，并且减少了自对准的难度。

公开(公告)号：US20090065846A1

公开(公告)日：2009-03-12

申请号：US11955396

申请日：2007-12-13

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7887

Abstract: A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure.

Abstract translation: 非易失性存储器的制造方法包括在衬底上依次形成第一电介质层，第一导电层和第一覆盖层，以形成第一栅极结构; 在基底上保形地形成第二电介质层; 在每个第一栅极结构的每个侧壁上形成具有比第二介电层更大的湿蚀刻速率的第一间隔物; 部分地去除第一和第二电介质层以暴露衬底。 在第一栅极结构之间的衬底上形成第三电介质层; 去除第一间隔物; 在所述第三介电层上形成第二导电层; 移除所述第一盖层和所述第一导电层的一部分以形成第二栅极结构; 以及在每个第二栅极结构的两侧在衬底中形成掺杂区域。

公开(公告)号：US20080315284A1

公开(公告)日：2008-12-25

申请号：US11953886

申请日：2007-12-11

Applicant: Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

Inventor： Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

IPC: H01L29/00 ,  H01L21/336

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

Abstract: A flash memory cell includes a substrate, a T-shaped control gate disposed above the substrate, a floating gate embedded in a lower recess of the T-shaped control gate, a dielectric layer between the T-shaped control gate and the floating gate; a cap layer above the T-shaped control gate, a control gate oxide between the T-shaped control gate and the substrate, a floating gate oxide between the floating gate and the substrate, a liner covering the cap layer and the floating gate, and a source/drain region adjacent to the floating gate. The floating gate has a vertical wall surface that is coplanar with one side of the dielectric layer.

Abstract translation: 闪存单元包括衬底，设置在衬底上方的T形控制栅极，嵌入在T形控制栅极的下凹槽中的浮置栅极，在T形控制栅极和浮置栅极之间的介电层; T形控制栅极上方的覆盖层，T形控制栅极和衬底之间的控制栅极氧化物，浮置栅极和衬底之间的浮置栅极氧化物，覆盖覆盖层和浮动栅极的衬底，以及 与浮动栅极相邻的源极/漏极区域。 浮动栅极具有与电介质层的一侧共面的垂直壁表面。

公开(公告)号：US20080296725A1

公开(公告)日：2008-12-04

申请号：US11955399

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

Inventor： Ching-Nan Hsiao ,  Chung-Lin Huang ,  Chen-Yu Tsai ,  Chung-Yuan Lee

IPC: H01L23/00 ,  H01L21/76

CPC classification number: H01L21/823481 ,  H01L27/11521

Abstract: A semiconductor component includes a substrate, two isolation structures, a conductor pattern and a dielectric layer. The isolation structures are disposed in the substrate, and each of the isolation structures has protruding portions protruding from the surface of the substrate. A trench is formed between the protruding portions. The included angle formed by the sidewall of the protruding portion and the surface of the substrate is an obtuse angle. The conductor pattern is disposed in the trench and fills the trench up. The dielectric layer is disposed between the conductor pattern and the substrate.

Abstract translation: 半导体部件包括基板，两个隔离结构，导体图案和电介质层。 隔离结构设置在基板中，并且每个隔离结构具有从基板的表面突出的突出部分。 在突出部之间形成沟槽。 由突出部分的侧壁和基板的表面形成的夹角是钝角。 导体图案设置在沟槽中并将沟槽填满。 电介质层设置在导体图案和基板之间。

公开(公告)号：US06855966B2

公开(公告)日：2005-02-15

申请号：US10435416

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L31/072 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521

Abstract: A floating gate and a fabricating method of the same. A semiconductor substrate is provided. A gate dielectric layer and a conducting layer are sequentially formed on the semiconductor substrate. A patterned hard mask layer having an opening is formed on the conducting layer, wherein a portion of the conducting layer is exposed through the opening. A spacer is formed on the sidewall of the opening. The patterned hard mask layer is removed. A conducting spacer is formed on the sidewall of the spacer. The exposed conducting layer and the exposed gate dielectric layer are sequentially removed.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底。 在半导体衬底上依次形成栅介电层和导电层。 在导电层上形成具有开口的图案化的硬掩模层，其中导电层的一部分通过开口露出。 间隔件形成在开口的侧壁上。 图案化的硬掩模层被去除。 导电间隔件形成在间隔件的侧壁上。 依次去除暴露的导电层和暴露的栅介质层。

公开(公告)号：US08604620B2

公开(公告)日：2013-12-10

申请号：US13342201

申请日：2012-01-03

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

IPC: H01L29/40

CPC classification number: H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2224/03

Abstract: The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.

Abstract translation: 本发明提供一种具有横向TSV的半导体结构及其制造方法。 半导体结构包括具有有源侧的芯片，与有源侧相对设置的背面以及设置在主动侧和后侧之间的侧面。 芯片还包括接触焊盘，横向TSV和图案化导电层。 接触垫设置在活动侧。 横向TSV设置在侧面。 图案化导电层设置在有源侧上并且电连接到侧向TSV和接触焊盘。

公开(公告)号：US20130113110A1

公开(公告)日：2013-05-09

申请号：US13342201

申请日：2012-01-03

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

IPC: H01L23/48 ,  H01L21/78

CPC classification number: H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/02371 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/08145 ,  H01L2224/08148 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2224/03

Abstract: The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.

Abstract translation: 本发明提供一种具有横向TSV的半导体结构及其制造方法。 半导体结构包括具有有源侧的芯片，与有源侧相对设置的背面以及设置在主动侧和后侧之间的侧面。 芯片还包括接触焊盘，横向TSV和图案化导电层。 接触垫设置在活动侧。 横向TSV设置在侧面。 图案化导电层设置在有源侧上并且电连接到侧向TSV和接触焊盘。

公开(公告)号：US08431933B2

公开(公告)日：2013-04-30

申请号：US12874232

申请日：2010-09-02

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC: H01L29/10

CPC classification number: H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

Abstract translation: 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

公开(公告)号：US08058136B2

公开(公告)日：2011-11-15

申请号：US12827082

申请日：2010-06-30

Applicant: Chien-Hsun Chen ,  Tzung Han Lee ,  Chung-Lin Huang

Inventor： Chien-Hsun Chen ,  Tzung Han Lee ,  Chung-Lin Huang

IPC: H01L21/76

CPC classification number: H01L27/10876 ,  H01L21/76224 ,  H01L27/10894

Abstract: A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.

Abstract translation: 用于凹槽通道动态随机存取存储器的自对准方法包括：提供具有目标层，阻挡层和衬里层的衬底，其中所述目标层具有浅沟槽隔离结构; 图案化衬里层，阻挡层和目标层以形成凹槽沟道; 将介电层沉积到凹槽沟道上; 在靶层中形成离子掺杂区; 去除所述电介质层的一部分以暴露所述凹槽沟槽沟道的一部分; 形成覆盖在所述凹槽沟道上的填充层; 去除所述填充层的一部分以暴露所述凹槽沟道的一部分; 在所述凹槽沟道上形成钝化层; 去除衬里层上的钝化层; 并且移除所述衬里层以形成设置在所述凹槽沟道处并从所述目标层突出的多个结构单体。

公开(公告)号：US08003480B2

公开(公告)日：2011-08-23

申请号：US12700796

申请日：2010-02-05

Applicant: Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer.

Abstract translation: 公开了一种使用氧化物载体制造微米堆叠DRAM的电容器下电极的方法。 首先，形成堆叠结构。 其次，在上部氧化物层上形成光致抗蚀剂层，然后蚀刻它们。 第三，将多晶硅层沉积到上氧化物层和氮化物层上。 第四，在多晶硅层和上部氧化物层上沉积氮氧化物层。 第六，部分地蚀刻氮氧化物层，多晶硅层和上部氧化物层以形成多个通孔。 第七，氧化多晶硅层以形成围绕通孔的多个二氧化硅。 第八，在通孔下方蚀刻氮化物层，介电层和低氧化物层。 第九，在每个通孔中形成金属板和电容器下电极。 第十，蚀刻氮氧化物层，多晶硅层，氮化物层和电介质层。