公开(公告)号：US07053453B2

公开(公告)日：2006-05-30

申请号：US10863600

申请日：2004-06-08

申请人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

发明人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L29/76

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.

摘要翻译： 基板接触和半导体芯片及其形成方法。 基板接触可以由半导体基板形成的半导体芯片使用，并且包括围绕集成电路区域的周边的密封环区域。 在一个实施例中，衬底接触包括延伸穿过浅沟槽隔离区域的接触沟槽和覆盖在半导体衬底上以及集成电路区域之外的绝缘体。 接触沟槽基本上填充有导电材料，从而允许半导体衬底与密封环区域内的金属互连电连接。

公开(公告)号：US20060051922A1

公开(公告)日：2006-03-09

申请号：US10937722

申请日：2004-09-09

申请人： Chien-Chao Huang ,  Cheng-Chuan Huang ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Cheng-Chuan Huang ,  Fu-Liang Yang

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/78621

摘要： A method of manufacturing a microelectronic device includes forming a p-channel transistor on a silicon substrate by forming a poly gate structure over the substrate and forming a lightly doped source/drain region in the substrate. An oxide liner and nitride spacer are formed adjacent to opposing side walls of the poly gate structure and a recess is etched in the semiconductor substrate on opposing sides of the oxide liner. Raised SiGe source/drain regions are formed on either side of the oxide liner and slim spacers are formed over the oxide liner. A hard mask over the poly gate structure is used to protect the poly gate structure during the formation of the raised SiGe source/drain regions. A source/drain dopant is then implanted into the substrate including the SiGe regions.

摘要翻译： 微电子器件的制造方法包括通过在衬底上形成多晶硅栅极结构并在衬底中形成轻掺杂的源极/漏极区，在硅衬底上形成p沟道晶体管。 邻近多晶硅栅极结构的相对侧壁形成氧化物衬垫和氮化物间隔物，并且在氧化物衬垫的相对侧上的半导体衬底中蚀刻凹陷。 在氧化物衬垫的两侧形成升高的SiGe源极/漏极区，并且在氧化物衬垫上形成细长的间隔物。 在形成升高的SiGe源极/漏极区域期间，使用多晶硅栅极结构上的硬掩模来保护多晶硅栅极结构。 然后将源极/漏极掺杂剂注入到包括SiGe区域的衬底中。

公开(公告)号：US20050236712A1

公开(公告)日：2005-10-27

申请号：US10863600

申请日：2004-06-08

申请人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

发明人： Hsun-Chih Tsao ,  Chien-Chao Huang ,  Fu-Liang Yang

IPC分类号： H01L23/00 ,  H01L23/52 ,  H01L23/58

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one embodiment, the substrate contact includes a contact trench extending through a shallow trench isolation region and an insulator overlying the semiconductor substrate and outside the integrated circuit region. The contact trench is substantially filled with a conductive material thereby allowing the semiconductor substrate to be electrically connected with a metal interconnect within the seal ring region.

摘要翻译： 基板接触和半导体芯片及其形成方法。 基板接触可以由半导体基板形成的半导体芯片使用，并且包括围绕集成电路区域的周边的密封环区域。 在一个实施例中，衬底接触包括延伸穿过浅沟槽隔离区域的接触沟槽和覆盖在半导体衬底上以及集成电路区域之外的绝缘体。 接触沟槽基本上填充有导电材料，从而允许半导体衬底与密封环区域内的金属互连电连接。

公开(公告)号：US20050230763A1

公开(公告)日：2005-10-20

申请号：US10824854

申请日：2004-04-15

申请人： Chien-Chao Huang ,  Cheng-Kuo Wen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Cheng-Kuo Wen ,  Fu-Liang Yang

IPC分类号： H01L21/8238 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823842 ,  H01L29/41791 ,  H01L29/7833 ,  H01L2029/7858

摘要： A method of manufacturing a microelectronic device. The method includes providing a substrate and forming a patterned feature located over the substrate and a plurality of doped regions. The patterned feature also comprises at least one electrode, wherein the electrode is proximate a plurality of doped layers. The method further includes forming a sill located within the electrode, wherein the sill comprising at least one impurity and adapted for modifying an electrical property of at least one member adjacent the electrode.

摘要翻译： 一种制造微电子器件的方法。 该方法包括提供衬底并形成位于衬底上方的图案化特征以及多个掺杂区域。 图案化特征还包括至少一个电极，其中电极接近多个掺杂层。 所述方法还包括形成位于所述电极内的基台，其中所述基底包括至少一种杂质并且适于改变邻近所述电极的至少一个构件的电性能。

公开(公告)号：US20050224867A1

公开(公告)日：2005-10-13

申请号：US10816089

申请日：2004-03-31

申请人： Chien-Chao Huang ,  Tone-Xuan Chung ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Tone-Xuan Chung ,  Fu-Liang Yang

IPC分类号： H01L21/324 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/78

CPC分类号： H01L29/6653 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

摘要： A CMOS structure including a Slim spacer and method for forming the same to reduce an S/D electrical resistance and improve charge mobility in a channel region, the method including providing a semiconductor substrate including a polysilicon gate structure including at least one overlying hardmask layer; forming spacers selected from the group consisting of oxide/nitride and oxide/nitride oxide layers adjacent the polysilicon gate structure; removing the at least one overlying hardmask layer to expose the polysilicon gate structure; carrying out an ion implant process; carrying out at least one of a wet and dry etching process to reduce the width of the spacers; and, forming at least one dielectric layer over the polysilicon gate structure and spacers in one of tensile and compressive stress.

摘要翻译： 包括Slim间隔物的CMOS结构及其形成方法以降低S / D电阻并改善沟道区中的电荷迁移率，所述方法包括提供包括至少一个上覆硬掩模层的多晶硅栅极结构的半导体衬底; 选自由邻近多晶硅栅极结构的氧化物/氮化物和氧化物/氮化物层组成的组中的间隔物; 去除所述至少一个覆盖的硬掩模层以暴露所述多晶硅栅极结构; 进行离子注入工艺; 执行湿式和干式蚀刻工艺中的至少一种以减小间隔物的宽度; 并且在多晶硅栅极结构和隔离物之间形成至少一个介电层，其中一个拉伸和压缩应力中的一个。

公开(公告)号：US20050212015A1

公开(公告)日：2005-09-29

申请号：US10810950

申请日：2004-03-25

申请人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

发明人： Chien-Chao Huang ,  Kuang-Hsin Chen ,  Fu-Liang Yang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/02

CPC分类号： H01L29/66553 ,  H01L21/28097 ,  H01L21/82345 ,  H01L21/823468 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.

摘要翻译： 一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。 形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。 这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。 然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。 然后金属层与栅电极反应形成金属栅极。

公开(公告)号：US08790970B2

公开(公告)日：2014-07-29

申请号：US11446697

申请日：2006-06-05

申请人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Ping-Wei Wang ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/84

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66803

摘要： A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

摘要翻译： 半导体结构包括覆盖绝缘体层的多个半导体鳍片，覆盖所述半导体鳍片的一部分的栅极电介质和覆盖栅极电介质的栅电极。 每个半导体翅片具有顶表面，第一侧壁表面和第二侧壁表面。 掺杂离子相对于半导体鳍片的顶表面的法线以第一角度（例如，大于约7°）注入，以掺杂第一侧壁表面和顶表面。 相对于半导体鳍片的顶表面的法线注入另外的掺杂剂离子以掺杂第二侧壁表面和顶表面。

公开(公告)号：US07319258B2

公开(公告)日：2008-01-15

申请号：US10901763

申请日：2004-07-28

申请人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Hung-Wei Chen ,  Tim Tsao ,  Chenming Hu

发明人： Fu-Liang Yang ,  Yee-Chia Yeo ,  Hung-Wei Chen ,  Tim Tsao ,  Chenming Hu

IPC分类号： H01L21/01 ,  H01L21/12

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/78654

摘要： A semiconductor-on-insulator device includes a silicon active layer with a crystal direction placed over an insulator layer. The insulator layer is placed onto a substrate with a crystal direction. Transistors oriented on a direction are formed on the silicon active layer.

摘要翻译： 绝缘体上半导体器件包括布置在绝缘体层上的具有<100>晶体方向的硅有源层。 将绝缘体层放置在具有<110>晶体方向的衬底上。 在硅有源层上形成沿<100>方向取向的晶体管。

公开(公告)号：US20070111454A1

公开(公告)日：2007-05-17

申请号：US11649453

申请日：2007-01-03

申请人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Hao-Yu Chen ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A method for forming a gate electrode for a multiple gate transistor provides a doped, planarized gate electrode material which may be patterned using conventional methods to produce a gate electrode that straddles the active area of the multiple gate transistor and has a constant transistor gate length. The method includes forming a layer of gate electrode material having a non-planar top surface, over a semiconductor fin. The method further includes planarizing and doping the gate electrode material, without doping the source/drain active areas, then patterning the gate electrode material. Planarization of the gate electrode material may take place prior to the introduction and activation of dopant impurities or it may follow the introduction arid activation of dopant impurities. After the gate electrode is patterned, dopant impurities are selectively introduced to the semiconductor fin to form source/drain regions.

摘要翻译： 用于形成多栅极晶体管的栅电极的方法提供掺杂的平面化栅电极材料，其可以使用常规方法进行图案化以产生跨越多栅极晶体管的有源区并具有恒定晶体管栅极长度的栅电极。 该方法包括在半导体鳍上形成具有非平面顶表面的栅电极材料层。 该方法还包括对栅电极材料进行平面化和掺杂，而不掺杂源极/漏极有源区，然后对栅电极材料进行构图。 栅电极材料的平面化可以在引入和激活掺杂剂杂质之前进行，或者可以引入和掺杂杂质的激活。 在栅电极被图案化之后，掺杂剂杂质被选择性地引入半导体鳍片以形成源极/漏极区域。

公开(公告)号：US07214991B2

公开(公告)日：2007-05-08

申请号：US10313887

申请日：2002-12-06

申请人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

发明人： Yee-Chia Yeo ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L29/76

CPC分类号： H01L27/1211 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： An inverter that includes a first multiple-gate transistor including a source connected to a power supply, a drain connected to an output terminal, and a gate electrode; a second multiple-gate transistor including a source connected to a ground, a drain connected to the output terminal, and a gate electrode; and an input terminal connected to the gate electrodes of the first and second multiple-gate transistors. Each of the first and second multiple-gate transistors may further include a semiconductor fin formed vertically on an insulating layer on top of a substrate, a gate dielectric layer overlying the semiconductor fin, and a gate electrode wrapping around the semiconductor fin separating the source and drain regions.

摘要翻译： 一种逆变器，包括：第一多栅极晶体管，其包括连接到电源的源极，连接到输出端子的漏极和栅极电极; 第二多栅极晶体管，其包括连接到地的源极，连接到输出端子的漏极和栅极电极; 以及连接到第一和第二多栅极晶体管的栅电极的输入端子。 第一和第二多栅极晶体管中的每一个还可以包括在衬底顶部的绝缘层上垂直形成的半导体鳍片，覆盖在半导体鳍片上的栅极电介质层，以及围绕分离源极的半导体鳍状物包围的栅电极，以及 漏区。