公开(公告)号：US20080237703A1

公开(公告)日：2008-10-02

申请号：US11692213

申请日：2007-03-28

申请人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Yi-Chun Lin ,  Chi-Chih Chen ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： An exemplary embodiment of a semiconductor device capable of high-voltage operation includes a substrate with a well region therein. A gate stack with a first side and a second side opposite thereto, overlies the well region. Within the well region, a doped body region includes a channel region extending under a portion of the gate stack and a drift region is adjacent to the channel region. A drain region is within the drift region and spaced apart by a distance from the first side thereof and a source region is within the doped body region near the second side thereof. There is no P-N junction between the doped body region and the well region.

摘要翻译： 能够进行高压操作的半导体器件的示例性实施例包括其中具有阱区的衬底。 具有与其相对的第一侧和第二侧的栅极堆叠覆盖在阱区域上。 在阱区内，掺杂体区域包括在栅叠层的一部分下延伸的沟道区，漂移区与沟道区相邻。 漏极区域在漂移区域内并与其第一侧隔开距离，并且源极区域在其第二侧附近的掺杂体区域内。 在掺杂体区和阱区之间不存在P-N结。

公开(公告)号：US20080191291A1

公开(公告)日：2008-08-14

申请号：US12100888

申请日：2008-04-10

申请人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Chen-Bau Wu ,  Chien-Shao Tang ,  Robin Hsieh ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/78

CPC分类号： H01L27/092 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835

摘要： A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

摘要翻译： 提供了适用于高压应用的晶体管。 晶体管形成在具有第一导电类型的深阱的衬底上。 形成第一导电类型的第一阱和第二导电类型的第二阱，使得它们不彼此紧邻。 第一导电类型和第二导电类型的阱可以同时形成用于低电压装置的各个孔。 以这种方式，高压器件可以与具有较少工艺步骤的低电压器件形成在相同的晶片上，从而降低成本和处理时间。 可以在与第二阱相对的一侧上邻近第一阱形成掺杂隔离阱以提供进一步的器件隔离。

公开(公告)号：US20080001189A1

公开(公告)日：2008-01-03

申请号：US11593424

申请日：2006-11-06

申请人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

发明人： Yu-Chang Jong ,  Ruey-Hsin Liu ,  Yueh-Chiou Lin ,  Shun-Liang Hsu ,  Chi-Hsuen Chang ,  Te-Yin Hsia

IPC分类号： H01L29/76

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/0692

摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

摘要翻译： 高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

公开(公告)号：US20070181941A1

公开(公告)日：2007-08-09

申请号：US11351154

申请日：2006-02-09

申请人： Yi-Chun Lin ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

发明人： Yi-Chun Lin ,  Kuo-Ming Wu ,  Ruey-Hsin Liu

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/42368 ,  H01L29/66681

摘要： High voltage semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device capable of high-voltage operation, comprising a substrate comprising a first well formed therein. A gate stack is formed overlying the substrate, comprising a gate dielectric layer and a gate electrode formed thereon. A channel well and a second well are formed in portions of the first well. A source region is formed in a portion of the channel well. A drain region is formed in a portion of the second well, wherein the gate dielectric layer comprises a relatively thinner portion at one end of the gate stack adjacent to the source region and a relatively thicker portion at one end of the gate stack adjacent to and directly contacts the drain region.

摘要翻译： 提供了高压半导体器件及其制造方法。 能够进行高压操作的半导体器件的示例性实施例，包括其中形成有第一阱的衬底。 形成覆盖在衬底上的栅叠层，包括形成在其上的栅介质层和栅电极。 在第一井的部分中形成通道井和第二井。 源区域形成在通道井的一部分中。 漏极区域形成在第二阱的一部分中，其中栅极电介质层包括邻近源极区域的栅极堆叠的一端处的相对较薄的部分，以及邻近栅极堆叠的一端的相对较厚的部分， 直接接触漏区。

公开(公告)号：US07250344B2

公开(公告)日：2007-07-31

申请号：US11272260

申请日：2005-11-10

申请人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

发明人： Kuan-Lun Chang ,  Ruey-Hsin Liu ,  Tsyr-Shyang Liou ,  Chih-Min Chiang ,  Jun-Lin Tsai

IPC分类号： H01L21/336

CPC分类号： H01L21/76232 ,  H01L21/763

摘要： A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.

摘要翻译： 提供了一种形成用于半导体器件的浅沟槽 - 深沟槽隔离的方法。

公开(公告)号：US07196375B2

公开(公告)日：2007-03-27

申请号：US10801234

申请日：2004-03-16

申请人： Fu-Hsin Chen ,  Ruey-Hsin Liu

发明人： Fu-Hsin Chen ,  Ruey-Hsin Liu

IPC分类号： H01L29/76

CPC分类号： H01L29/66575 ,  H01L29/66659

摘要： A method for fabricating a high-voltage MOS transistor. A first doping region with a first dosage is formed in a substrate. A gate structure is formed overlying the substrate and partially covers the first doping region. The substrate is ion implanted using the gate structure as a mask to simultaneously form a second doping region with a second dosage within the first doping region to serve as a drain region and form a third doping region with the second dosage in the substrate to serve as a source region. A channel region is formed in the substrate between the first and third doping regions when the high-voltage MOS transistor is turned on to pass current between the source and drain regions, where a resistance per unit length of the channel region is substantially equal to that of the first doping region. A high-voltage MOS transistor is also disclosed.

摘要翻译： 一种用于制造高压MOS晶体管的方法。 在衬底中形成具有第一剂量的第一掺杂区域。 栅极结构形成在衬底上并部分地覆盖第一掺杂区域。 使用栅极结构作为掩模离子注入衬底，以在第一掺杂区域内同时形成具有第二剂量的第二掺杂区域，以用作漏极区域，并形成第二掺杂区域，第二掺杂区域在衬底中用作第二掺杂区域，以用作 源区域。 当高电压MOS晶体管导通时，沟道区形成在第一和第三掺杂区之间的衬底中，以在源极和漏极区之间传导电流，其中沟道区的每单位长度的电阻基本上等于 的第一个掺杂区域。 还公开了高压MOS晶体管。

公开(公告)号：US20050285218A1

公开(公告)日：2005-12-29

申请号：US10877450

申请日：2004-06-25

申请人： Kuo-Ming Wu ,  Chen-Bau Wu ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

发明人： Kuo-Ming Wu ,  Chen-Bau Wu ,  Ruey-Hsin Liu ,  Shun-Liang Hsu

IPC分类号： H01L29/00 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/7835

摘要： A high voltage device with retrograde well is disclosed. The device comprises a substrate, a gate region formed on the substrate, and a retrograde well placed in the substrate next to the gate region, wherein the retrograde well reduces a dopant concentration on the surface of the substrate, thereby minimizing damages to the gate region.

摘要翻译： 公开了具有逆行井的高压装置。 该器件包括衬底，形成在衬底上的栅极区域和位于栅极区域旁边的衬底中的逆行阱，其中逆行阱降低衬底表面上的掺杂剂浓度，从而最小化对栅极区域的损害 。

公开(公告)号：US6165861A

公开(公告)日：2000-12-26

申请号：US152348

申请日：1998-09-14

申请人： Ruey-Hsin Liu ,  Jun-Lin Tsai ,  Yung-Lung Hsu

发明人： Ruey-Hsin Liu ,  Jun-Lin Tsai ,  Yung-Lung Hsu

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L27/0802

摘要： A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.

摘要翻译： 通过使用防止氢进入电阻器的硅化物层来实现稳定的高价值多晶硅电阻器。 电阻器也可以集成到自对准硅化物工艺中，用于制造FET而不增加工艺复杂性。 图案化具有帽氧化物的多晶硅层以形成FET栅电极和多晶硅电阻器。 形成了用于FET的轻掺杂源极/漏极，绝缘侧壁间隔物和源极/漏极接触。 盖帽氧化物被图案化以暴露电阻器的一端，并且帽状氧化物从栅电极移除。 沉积和退火难熔金属以形成硅化物FET并同时在电阻器的末端形成硅化物。 未反应的金属被蚀刻。 沉积层间电介质层，并且在电阻器的两端形成与金属插塞的接触孔。 沉积金属以形成第一级金属互连，其也提供与电阻器两端的接触。 金属也被图案化以在电阻器上形成金属屏蔽，以防止氢扩散到电阻器中。 在本发明中，接触电阻器端部的金属部分之间的间隔在电阻器上的硅化物上排列，以提供100％的阻挡氢扩散到电阻器中的屏蔽。

公开(公告)号：US08921934B2

公开(公告)日：2014-12-30

申请号：US13546738

申请日：2012-07-11

申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Po-Chih Su ,  Ruey-Hsin Liu

IPC分类号： H01L29/66

CPC分类号： H01L29/401 ,  H01L29/0684 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66704 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7856

摘要： An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

摘要翻译： 一种集成电路器件包括：衬垫层，其具有主体部分，该主体部分具有横向邻近具有第二掺杂类型的漂移区域部分的第一掺杂型，形成在焊盘层中的沟槽，沟槽延伸穿过主体部分的界面和 漂移区部分，形成在沟槽中的栅极和沿着主体部分和漂移区部分的界面的焊盘层的顶表面上的栅极，形成在栅极的相对侧上的沟槽中的氧化物和嵌入的场板 在栅极的每个相对侧上的氧化物中。

公开(公告)号：US08884369B2

公开(公告)日：2014-11-11

申请号：US13486633

申请日：2012-06-01

申请人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Po-Chih Su

发明人： Chun-Wai Ng ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu ,  Po-Chih Su

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/823425 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7827 ,  H01L29/7831

摘要： A device includes a semiconductor layer of a first conductivity type, and a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite the first conductivity type. A doped semiconductor region of the first conductivity type is disposed between and contacting the first and the second body regions. A gate dielectric layer is disposed over the first and the second body regions and the doped semiconductor region. A first and a second gate electrode are disposed over the gate dielectric layer, and overlapping the first and the second body regions, respectively. The first and the second gate electrodes are physically separated from each other by a space, and are electrically interconnected. The space between the first and the second gate electrodes overlaps the doped semiconductor region.

摘要翻译： 一种器件包括第一导电类型的半导体层以及半导体层上的第一和第二体区，其中第一和第二体区具有与第一导电类型相反的第二导电类型。 第一导电类型的掺杂半导体区域设置在第一和第二主体区域之间并且与第一和第二主体区域接触。 栅极电介质层设置在第一和第二主体区域和掺杂半导体区域上。 第一和第二栅极设置在栅极介电层上方，分别与第一和第二体区重叠。 第一和第二栅电极在物理上彼此分开一个空间，并被电互连。 第一和第二栅电极之间的空间与掺杂半导体区域重叠。