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97 条记录 (耗时 0.027 秒)

    [METAL SILICIDE STRUCTURE AND METHOD OF FORMING THE SAME]
    53.
    发明申请
    [METAL SILICIDE STRUCTURE AND METHOD OF FORMING THE SAME] 审中-公开
    [金属硅化物结构及其形成方法]

    公开(公告)号：US20050009337A1

    公开(公告)日：2005-01-13

    申请号：US10604835

    申请日：2003-08-21

    申请人： Hung-Wei Liu ,  Kuang-Chao Chen ,  Hsueh-Hao Shih

    发明人： Hung-Wei Liu ,  Kuang-Chao Chen ,  Hsueh-Hao Shih

    IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/44

    CPC分类号： H01L21/28518

    摘要： A method of forming a suicide layer is described. A silicon layer is provided. Ions are introduced in the silicon layer. A metal layer is formed on the silicon layer. An annealing process is performed so that the silicon layer reacts with the metal layer to form the metal silicide layer. Thereafter, the unreacted metal layer is removed. The uniformity of the grain size and the grain distribution of the metal silicide layer are improved by introducing the ions in the silicon layer before performing the annealing process, so that sheet resistance of the metal silicide layer is reduced.

    摘要翻译： 描述了形成硅化物层的方法。 提供硅层。 硅在硅层中引入了离子。 在硅层上形成金属层。 执行退火处理，使得硅层与金属层反应以形成金属硅化物层。 之后，除去未反应的金属层。 在进行退火处理之前，通过在硅层中引入离子来改善金属硅化物层的晶粒尺寸和晶粒分布的均匀性，从而降低金属硅化物层的薄层电阻。

    Method of fabricating a capacitor on a rugged stacked oxide layer
    54.
    发明授权
    Method of fabricating a capacitor on a rugged stacked oxide layer 失效
    在坚固的堆叠氧化物层上制造电容器的方法

    公开(公告)号：US5960279A

    公开(公告)日：1999-09-28

    申请号：US697622

    申请日：1996-08-27

    申请人： Kuang-Chao Chen ,  Tuby Tu

    发明人： Kuang-Chao Chen ,  Tuby Tu

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L27/10852 ,  H01L28/84

    摘要： The present invention relates to a stacked memory capacitor of a DRAM cell, particularly, relates to a DRAM cell having a memory capacitor whose storage electrode possesses a remarkably increase area without increasing its occupation area and the complexity of fabrication thereof. By disposing the storage electrode of the memory capacitor on a rugged stacked oxide layer, the area of the storage electrode is remarkably enlarged since the growing of the storage electrode made of a doped polysilicon layer is followed along the topography of the rugged stacked oxide layer, thereby, resulting in a rugged surface thereof. The entire rugged surface of the storage electrode is covered with a dielectric layer to form a plate electrode made of a doped polysilicon layer. The memory capacitor provided by the invention achieves a higher capacitance while maintaining the same occupation area and packing density as that of the conventional arts.

    摘要翻译： 本发明涉及一种DRAM单元的堆叠式存储电容器，特别涉及一种具有存储电容器的存储电容器的DRAM单元，其存储电极具有显着增加的面积而不增加其占用面积及其制造的复杂性。 通过将存储电容器的存储电极设置在坚固的堆叠氧化物层上，由于沿着凹凸的堆叠氧化物层的形貌遵循由掺杂多晶硅层制成的存储电极的生长，所以存储电极的面积显着增大， 从而导致其表面粗糙。 存储电极的整个粗糙表面被电介质层覆盖以形成由掺杂多晶硅层制成的平板电极。 本发明提供的存储电容器在保持与传统技术相同的占用面积和封装密度的同时实现更高的电容。

    Method for using oxygen plasma treatment on a dielectric layer
    55.
    发明授权
    Method for using oxygen plasma treatment on a dielectric layer 失效
    在电介质层上使用氧等离子体处理的方法

    公开(公告)号：US5883015A

    公开(公告)日：1999-03-16

    申请号：US887886

    申请日：1997-07-03

    申请人： Kent Liao ,  Dinos Huang ,  Tuby Tu ,  Kuang-Chao Chen ,  Wen-Doe Su

    发明人： Kent Liao ,  Dinos Huang ,  Tuby Tu ,  Kuang-Chao Chen ,  Wen-Doe Su

    IPC分类号： C23C16/40 ,  H01L21/314 ,  H01L21/316

    CPC分类号： H01L21/02164 ,  C23C16/402 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

    摘要： The method for depositing a dielectric layer can be used to evenly deposit the dielectric layer to be applied to a semiconductor device. The method includes steps of: a) providing a substrate; b) depositing a first dielectric film on the subtrate; c) introducing an oxygen plasma for eliminating an uneven distribution of charges on a surface of the substrate; and d) forming a second dielectric film on the first dielectric film treated with the oxygen plasma for obtaining the dielectric layer having a uniform thickness on the substrate,

    摘要翻译： 用于沉积电介质层的方法可用于均匀地沉积要施加到半导体器件的介质层。 该方法包括以下步骤：a）提供衬底; b）在所述缓冲液上沉积第一介电膜; c）引入氧等离子体以消除基板表面上电荷的不均匀分布; 以及d）在用氧等离子体处理的第一电介质膜上形成第二电介质膜，以获得在衬底上具有均匀厚度的电介质层，

    Method of reducing wordline shorting
    57.
    发明授权
    Method of reducing wordline shorting 有权
    减少字线短路的方法

    公开(公告)号：US08445346B2

    公开(公告)日：2013-05-21

    申请号：US12611614

    申请日：2009-11-03

    申请人： Hong-Ji Lee ,  Nan-Tsu Lian ,  Kuang-Chao Chen

    发明人： Hong-Ji Lee ,  Nan-Tsu Lian ,  Kuang-Chao Chen

    IPC分类号： H01L21/8247

    CPC分类号： H01L21/28247 ,  H01L21/28282 ,  H01L27/11568

    摘要： A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface.

    摘要翻译： 一种制造存储器件的方法包括提供具有绝缘层的衬底，在绝缘层上形成第一，第二和第三导电层，在第三导电层上形成掩模，蚀刻通过第三导电层和第一部分厚度 使用所述掩模提供所述第三导电层的蚀刻侧壁部分和所述第二多晶硅层的蚀刻的上表面，以及沿着蚀刻的侧壁部分和所蚀刻的上表面形成衬垫层。

    Method for forming self-aligned contacts and local interconnects simultaneously
    59.
    发明授权
    Method for forming self-aligned contacts and local interconnects simultaneously 有权
    同时形成自对准触点和局部互连的方法

    公开(公告)号：US07888804B2

    公开(公告)日：2011-02-15

    申请号：US12113855

    申请日：2008-05-01

    申请人： Tuung Luoh ,  Ling-Wuu Yang ,  Kuang-Chao Chen

    发明人： Tuung Luoh ,  Ling-Wuu Yang ,  Kuang-Chao Chen

    IPC分类号： H01L23/48

    CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115

    摘要： The present invention relates generally to semiconductors, and more specifically to semiconductor memory device structures and an improved fabrication process for making the same. The improved fabrication process allows the self-aligned contacts and local interconnects to the processed simultaneously. The process allows the minimal distance requirement between the self-aligned contacts and the local interconnects to be widened, which makes the patterning of self-aligned contacts and local interconnects easier. The widened minimal distance requirement also allows further memory cell shrinkage. The improved structures of self-aligned contacts and local interconnects also have excellent isolation characteristic.

    摘要翻译： 本发明一般涉及半导体，更具体地涉及半导体存储器件结构和改进的制造方法。 改进的制造工艺允许自对准触点和局部互连同时处理。 该过程允许自对准触点和局部互连之间的最小距离要求加宽，这使得自对准触点和局部互连的图案化变得更容易。 扩大的最小距离要求也允许进一步的记忆体细胞收缩。 自对准触点和局部互连的改进结构也具有优异的隔离特性。