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    Maskless inter-well deep trench isolation structure and methods of manufacture
    51.
    发明授权
    Maskless inter-well deep trench isolation structure and methods of manufacture 有权
    无掩膜深沟槽隔离结构及制造方法

    公开(公告)号：US08536018B1

    公开(公告)日：2013-09-17

    申请号：US13467314

    申请日：2012-05-09

    申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

    发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

    IPC分类号： H01L27/108

    CPC分类号： H01L21/76283 ,  H01L21/76232 ,  H01L21/84

    摘要： A low power maskless inter-well deep trench isolation structure and methods of manufacture such structure are provided. A method includes depositing a plurality of layers over a substrate, and forming a layer over the plurality of layers. The method also includes forming well structures in the substrate, and forming sidewall spacers at opposing sides of the layer. The method further includes forming a self-aligned deep trench in the substrate to below the well structures, by removing the sidewall spacers and portions of the substrate aligned with an opening formed by the removal of the sidewall spacers. The method also includes forming a shallow trench in alignment with the deep trench. The method further includes forming shallow trench isolation structures and deep trench isolation structures by filling the shallow trench and the deep trench with insulator material.

    摘要翻译： 提供了一种低功率无掩膜深沟槽隔离结构及其制造方法。 一种方法包括在衬底上沉积多个层，并在多个层上形成层。 该方法还包括在衬底中形成阱结构，以及在层的相对侧形成侧壁间隔物。 该方法还包括通过去除侧壁间隔件和与通过去除侧壁间隔件形成的开口对准的衬底的部分，将衬底中的自对准深沟槽形成在阱结构下方。 该方法还包括形成与深沟槽对准的浅沟槽。 该方法还包括通过用绝缘体材料填充浅沟槽和深沟槽来形成浅沟槽隔离结构和深沟槽隔离结构。

    Formation of Field Effect Transistor Devices
    53.
    发明申请
    Formation of Field Effect Transistor Devices 有权

    公开(公告)号：US20120329227A1

    公开(公告)日：2012-12-27

    申请号：US13605136

    申请日：2012-09-06

    申请人： Josephine B. Chang ,  Paul C. Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

    发明人： Josephine B. Chang ,  Paul C. Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

    IPC分类号： H01L21/336

    CPC分类号： H01L27/0207 ,  H01L29/66545

    摘要： A method includes defining active regions on a substrate, forming a dummy gate stack material over exposed portions of the active regions of the substrate and non-active regions of the substrate, removing portions of the dummy gate stack material to expose portions of the active regions and non-active regions of the substrate and define dummy gate stacks, forming a gap-fill dielectric material over the exposed portions of the substrate and the source and drain regions, removing portions of the gap-fill dielectric material to expose the dummy gate stacks, removing the dummy gate stacks to form dummy gate trenches, forming dividers within the dummy gate trenches, depositing gate stack material inside the dummy gate trenches, over the dividers, and the gap-fill dielectric material, and removing portions of the gate stack material to define gate stacks.

    COLLAPSABLE GATE FOR DEPOSITED NANOSTRUCTURES
    54.
    发明申请
    COLLAPSABLE GATE FOR DEPOSITED NANOSTRUCTURES 失效
    沉积式纳米结构的可收缩门

    公开(公告)号：US20120326127A1

    公开(公告)日：2012-12-27

    申请号：US13169542

    申请日：2011-06-27

    申请人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

    发明人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Philip S. Waggoner

    IPC分类号： H01L51/10 ,  H01L51/40

    CPC分类号： H01L29/66045 ,  H01L51/055

    摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

    摘要翻译： 一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。 一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。 通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。 一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。 然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。 独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION
    55.
    发明申请
    SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION 有权
    用于高密度电子和存储器件集成的自对准无边界联系

    公开(公告)号：US20100038723A1

    公开(公告)日：2010-02-18

    申请号：US12193339

    申请日：2008-08-18

    申请人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    发明人： Katherina E. Babich ,  Josephine B. Chang ,  Nicholas C. Fuller ,  Michael A. Guillorn ,  Isaac Lauer ,  Michael J. Rooks

    IPC分类号： H01L29/00 ,  H01L21/20

    CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.

    摘要翻译： 公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

    METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL
    56.
    发明申请
    METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL 审中-公开
    制备记忆细胞的双深度分离分离区的方法

    公开(公告)号：US20090269897A1

    公开(公告)日：2009-10-29

    申请号：US12111266

    申请日：2008-04-29

    申请人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

    发明人： Brent A. Anderson ,  Andres Bryant ,  Josephine B. Chang ,  Michael A. Guillorn ,  Ryoji Hasumi ,  Edward J. Nowak ,  Mickey H. Yu

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823481 ,  H01L27/1104

    摘要： Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.

    摘要翻译： 用于制造用于存储单元的双深度沟槽隔离区域的方法。 在半导体层中形成第一和第二深沟槽隔离区域，该半导体层横向地限定半导体层中的第一导电类型的阱中的器件区域。 在器件区域中形成第二导电类型的第一和第二多个掺杂区域。 形成了浅沟槽隔离区域，其横跨穿过器件区域从第一深沟槽隔离区域延伸到第二深沟槽隔离区域。 浅沟槽隔离区设置在第一和第二多个掺杂区域之间的器件区域中。 浅沟槽隔离区域延伸到半导体层中的深度，使得阱在浅沟槽隔离区域之下是连续的。 栅极堆叠控制一对第一多个掺杂区域之间的载流子流动。

    Embedded planar source/drain stressors for a finFET including a plurality of fins
    58.
    发明授权
    Embedded planar source/drain stressors for a finFET including a plurality of fins 有权
    用于包括多个翅片的finFET的嵌入式平面源极/漏极应力源

    公开(公告)号：US09024355B2

    公开(公告)日：2015-05-05

    申请号：US13483200

    申请日：2012-05-30

    申请人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

    发明人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Jeffrey W. Sleight

    IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66484 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848 ,  H01L29/785

    摘要： Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

    摘要翻译： 翅片限定掩模结构形成在具有第一半导体材料的半导体材料层上，并且在其上形成一次性栅极结构。 在一次性栅极结构周围形成栅极间隔物，随后去除鳍状物限定掩模结构的物理暴露部分。 使用一次性栅极结构和栅极间隔物作为蚀刻掩模来凹入半导体材料层以形成凹入的半导体材料部分。 通过选择性沉积具有与第一半导体材料不同的晶格常数的第二半导体材料，在凹入的半导体材料部分上形成嵌入式平面源极/漏极应力。 在形成平坦化介电层之后，去除一次性栅极结构。 使用鳍状限定掩模结构作为蚀刻掩模形成多个半导体鳍。 在多个半导体鳍片上形成替换栅极结构。

    Recessed source and drain regions for FinFETs
    59.
    发明授权
    Recessed source and drain regions for FinFETs 有权
    嵌入式FinFET的源极和漏极区域

    公开(公告)号：US08981478B2

    公开(公告)日：2015-03-17

    申请号：US13611335

    申请日：2012-09-12

    申请人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    发明人： Josephine B. Chang ,  Paul Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/785

    摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.

    摘要翻译： 半导体器件和方法包括通过在半导体层上限定翅片硬掩模来形成鳍状场效应晶体管，在散热片硬掩模上形成虚拟结构，以在半导体层上建立平面区域，去除超出鳍片硬掩模的一部分 蚀刻与虚拟结构相邻的半导体层，以产生凹陷的源极和漏极区域，去除虚设结构，蚀刻平面区域中的半导体层以产生鳍片，以及在鳍片上形成栅极叠层。