公开(公告)号：US07075413B2

公开(公告)日：2006-07-11

申请号：US11121909

申请日：2005-05-03

申请人： Daniel J. Friedman

发明人： Daniel J. Friedman

IPC分类号： H04Q5/22 ,  G05F3/02

CPC分类号： G06K19/0723

摘要： A passive RF tag is disclosed in which the tag contains a tag oscillator for determining the modulation frequency of modulating the backscatter signal, and the tag oscillator frequency is stabilized when the tag modulates the backscatter signal.

摘要翻译： 公开了一种无源RF标签，其中标签包含用于确定调制后向散射信号的调制频率的标签振荡器，并且当标签调制后向散射信号时，标签振荡器频率被稳定。

公开(公告)号：US06906615B2

公开(公告)日：2005-06-14

申请号：US10386138

申请日：2003-03-11

申请人： Daniel J. Friedman

发明人： Daniel J. Friedman

IPC分类号： G06K19/07 ,  H04Q5/22

CPC分类号： G06K19/0723

摘要： A passive RF tag is disclosed in which the tag contains a tag oscillator for determining the modulation frequency of modulating the backscatter signal, and the tag oscillator frequency is stabilized when the tag modulates the backscatter signal.

摘要翻译： 公开了一种无源RF标签，其中标签包含用于确定调制后向散射信号的调制频率的标签振荡器，并且当标签调制后向散射信号时，标签振荡器频率被稳定。

公开(公告)号：US06768414B2

公开(公告)日：2004-07-27

申请号：US09382382

申请日：1999-08-24

申请人： Harley Kent Heinrich ,  Christian Lenz Cesar ,  Thomas A. Cofino ,  Daniel J. Friedman ,  Kenneth Alan Goldman ,  Sharon Louise Greene ,  Kevin P. McAuliffe

发明人： Harley Kent Heinrich ,  Christian Lenz Cesar ,  Thomas A. Cofino ,  Daniel J. Friedman ,  Kenneth Alan Goldman ,  Sharon Louise Greene ,  Kevin P. McAuliffe

IPC分类号： H04Q522

CPC分类号： G07C3/00 ,  G06K7/0008 ,  G06K7/10039 ,  G06K7/10108 ,  G06K2017/0048 ,  G07C9/00111 ,  G08C2201/20

摘要： A Write Broadcast system and method uses a base station to write sent data to all or some selected number (sub group) of tags in a base station field simultaneously. By unselecting the tags that have been successfully written to, and requesting a response from the remaining tags in the field (or sub group), the system determines, by receiving a response to the request, that there are tags in the field (sub group) that were unsuccessfully written to. Another Write Broadcast signal is sent to these tags. The system is useful for quickly (simultaneously) “stamping” information on the tag memory of a large number of tags in the field of the base station.

摘要翻译： 写广播系统和方法使用基站将发送的数据同时写入基站字段中的所有或某些选定号码（子组）的标签。 通过取消选择已成功写入的标签，并请求来自字段（或子组）中的其余标签的响应，系统通过接收对该请求的响应来确定在该字段（子组）中存在标签 ）没有成功。 另一个写广播信号被发送到这些标签。 该系统对于在基站领域中的大量标签的标签存储器上快速（同时）“冲压”信息是有用的。

公开(公告)号：US06593845B1

公开(公告)日：2003-07-15

申请号：US09407919

申请日：1999-09-29

申请人： Daniel J. Friedman ,  Thomas Anthony Cofino ,  Trieu C. Chieu

发明人： Daniel J. Friedman ,  Thomas Anthony Cofino ,  Trieu C. Chieu

IPC分类号： H04Q522

CPC分类号： G06K19/0705 ,  G06K19/0701 ,  G06K19/0723 ,  G07C2009/00793

摘要： An active RF transponder is provided with a wake-up circuit that wakes the RF transponder from a sleep state upon detection of an RF interrogating signal. The active RF transponder includes a battery, an antenna adapted to receive RF signals from an interrogator, and electronic circuitry providing the various RF transponder functions of sending/receiving signals and storing data. A first embodiment of the invention includes a wake-up circuit that periodically checks for the presence of an RF signal at the antenna. The wake-up circuit is coupled to the antenna and includes a switch adapted to selectively couple the battery to the electronic circuitry and provide electrical power thereto upon detection of the RF signals by the antenna. The wake-up circuit further comprises an oscillator providing a clock signal having a low duty cycle that defines intervals during which the antenna is sampled for presence of the RF signals (e.g., approximately 20 ns every 100 &mgr;s). A second embodiment of the RF transponder includes a wake-up circuit as in the first embodiment that is further adapted to detect a code sequence modulated in the RF signals. The code sequence is unique for a class of RF transponder, so the wake-up circuit can discriminate between interrogating signals. A third embodiment of the RF transponder includes a wake-up circuit that wakes the RF transponder upon detection of an RF signal that contains data within a desired band of frequencies. This embodiment enables the RF transponder to discriminate between RF signals that likely contain valid data and other RF noise. After the RF transponder has been waked, the wake-up circuit returns the RF transponder to a sleep state if valid data is not detected within a predetermined period of time.

摘要翻译： 主动RF转发器具有唤醒电路，该唤醒电路在检测到RF询问信号时将RF应答器从睡眠状态唤醒。 主动RF转发器包括电池，适于从询问器接收RF信号的天线以及提供发送/接收信号和存储数据的各种RF应答器功能的电子电路。 本发明的第一实施例包括周期性地检查天线处的RF信号的存在的唤醒电路。 唤醒电路耦合到天线，并且包括开关，其适于在通过天线检测到RF信号时选择性地将电池耦合到电子电路并提供电力。 唤醒电路还包括振荡器，其提供具有低占空比的时钟信号，该时钟信号限定天线被采样以在RF信号的存在期间的间隔（例如，每100微秒大约20ns）。 RF转发器的第二实施例包括如第一实施例中的唤醒电路，其进一步适于检测在RF信号中调制的码序列。 代码序列对于一类RF转发器是唯一的，因此唤醒电路可以区分询问信号。 RF转发器的第三实施例包括唤醒电路，其在检测到包含期望频带中的数据的RF信号时唤醒RF应答器。 该实施例使得RF应答器能够区分可能包含有效数据的RF信号和其他RF噪声。 在RF应答器已经被唤醒之后，如果在预定时间段内没有检测到有效数据，则唤醒电路将RF应答器返回到睡眠状态。

公开(公告)号：US06412086B1

公开(公告)日：2002-06-25

申请号：US09323429

申请日：1999-06-01

申请人： Daniel J. Friedman ,  David E. Dieska

发明人： Daniel J. Friedman ,  David E. Dieska

IPC分类号： G01R3128

CPC分类号： G06K7/0095 ,  G01R31/3025 ,  G06K19/0723 ,  G06K19/073

摘要： A radio frequency identification (RFID) transponder (tag) integrated circuit includes “on-chip” test circuitry. The test circuitry includes a serially-loaded test register. The test register controls the execution of on-chip tests. Such tests may include the testing of EEPROM circuitry included within the IC, the testing of analog circuitry, or the testing of digital circuitry included within the IC.

摘要翻译： 射频识别（RFID）应答器（标签）集成电路包括“片上”测试电路。 测试电路包括一个串行测试寄存器。 测试寄存器控制片上测试的执行。 这样的测试可以包括对IC内包括的EEPROM电路的测试，模拟电路的测试或IC内包括的数字电路的测试。

公开(公告)号：US6078845A

公开(公告)日：2000-06-20

申请号：US756296

申请日：1996-11-25

申请人： Daniel J. Friedman

发明人： Daniel J. Friedman

IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L21/02 ,  H01L21/673 ,  G06F19/00

CPC分类号： H01L21/67288 ,  H01L21/67282 ,  H01L21/67326 ,  H01L21/67333 ,  H01L2221/68313 ,  Y10S438/907 ,  Y10S438/925

摘要： This invention pertains to the embedding of a information storage device within, or attached to, the carriers used to transport work in progress from step to step in the semiconductor manufacturing process. The carrier can be a tray having sites for several semiconductor dies, tubes for carrying several dies together, lead frames, wafer cassettes or individual die sockets. The information storage device can be formed integrally with the carrier or formed separately and attached or secured to the carrier.

摘要翻译： 本发明涉及将信息存储装置嵌入或附加到用于在半导体制造过程中逐步运行的工作的载体。 载体可以是具有用于多个半导体管芯的位置的托盘，用于将多个管芯携带在一起的管，引线框架，晶片盒或单个管芯插座。 信息存储装置可以与载体一体地形成或单独形成并且附接或固定到载体上。

公开(公告)号：US09269042B2

公开(公告)日：2016-02-23

申请号：US12895791

申请日：2010-09-30

申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04 ,  G11C11/54 ,  G11C13/00

CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

公开(公告)号：US08736323B2

公开(公告)日：2014-05-27

申请号：US11622166

申请日：2007-01-11

申请人： Woogeun Rhee ,  Daniel J. Friedman

发明人： Woogeun Rhee ,  Daniel J. Friedman

IPC分类号： H03L7/06

CPC分类号： G01R31/31709

摘要： An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

摘要翻译： 一种装置包括锁相环（PLL）电路，其包括被配置为输出相位误差信号的相位频率检测器。 相位误差监视电路被配置为通过逻辑组合相位误差信号并将逻辑组合相位误差信号的脉冲宽度与每个参考时钟周期的可编程延迟时间进行逻辑组合来确定瞬时峰值相位误差，以确定瞬时相位误差变化。 存储元件被配置为存储瞬时相位误差变化。

公开(公告)号：US20140070855A1

公开(公告)日：2014-03-13

申请号：US13608277

申请日：2012-09-10

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/107

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

公开(公告)号：US08665034B2

公开(公告)日：2014-03-04

申请号：US13245409

申请日：2011-09-26

申请人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03B5/08

CPC分类号： H03L7/099 ,  H03L2207/50

摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tuning steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.

摘要翻译： 公开了用于改进变容二极管电路调谐控制的技术。 例如，一种装置包括用于调谐频率值的多个变容二极管。 多个变容二极管包括大约sqrt（2N）变容二极管，其中N是多个调谐步骤，并且多个变容二极管的尺寸分别为1x，2x，3x，4x。 。 。 ，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。 这可以称为冗余编号。