公开(公告)号：US09203159B2

公开(公告)日：2015-12-01

申请号：US13371924

申请日：2012-02-13

申请人： Daniel J. Friedman ,  Xiaoxiong Gu ,  Duixian Liu ,  Arun S. Natarajan ,  Scott K. Reynolds ,  Alberto Valdes Garcia

发明人： Daniel J. Friedman ,  Xiaoxiong Gu ,  Duixian Liu ,  Arun S. Natarajan ,  Scott K. Reynolds ,  Alberto Valdes Garcia

IPC分类号： H01Q1/24 ,  H01Q21/06

CPC分类号： H01Q21/061 ,  H01L2224/16225 ,  H01Q21/065 ,  H01Q23/00 ,  H04B7/04 ,  Y10T29/49016

摘要： Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.

摘要翻译： 公开了针对收发器设备的系统，方法，设备和设备。 根据一种方法，选择电路封装的电路布局的一组部分的第一部分中的第一组天线位置。 该方法还包括在电路布局的另一部分中选择另一组天线位置，使得另一组的所选择的天线位置的布置与先前选择的一组天线位置的选定天线位置的布置不同。 迭代在另一部分中选择另一组位置，直到对天线总数进行选择。 执行另一组的选择，使得另一部分中的连续未选定位置不超过预定数量的位置。 此外，天线元件形成在所选择的位置以制造电路封装。

公开(公告)号：US08898097B2

公开(公告)日：2014-11-25

申请号：US13587594

申请日：2012-08-16

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

公开(公告)号：US08856055B2

公开(公告)日：2014-10-07

申请号：US13083414

申请日：2011-04-08

申请人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. Brezzo ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/063 ,  G06N3/04

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

公开(公告)号：US08779865B2

公开(公告)日：2014-07-15

申请号：US13350981

申请日：2012-01-16

申请人： Herschel A. Ainspan ,  John F. Bulzacchelli ,  Daniel J. Friedman ,  Ankush Goel ,  Alexander V. Rylyakov

发明人： Herschel A. Ainspan ,  John F. Bulzacchelli ,  Daniel J. Friedman ,  Ankush Goel ,  Alexander V. Rylyakov

IPC分类号： H03B5/12 ,  H03L7/10

CPC分类号： H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1256 ,  H03B5/1265 ,  H03B2200/0088 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L2207/06 ,  H03L2207/50

摘要： A design for an oscillator, and a PLL incorporating such an oscillator, which takes up little physical area but maintains a large tuning range and low phase noise. Two LC-tanks are nested and switched. Through tuning the inactive tank, the range of the active tank may be increased and finer tuning becomes possible.

摘要翻译： 振荡器的设计，以及包含这种振荡器的PLL，其占用很小的物理面积，但保持较大的调谐范围和低的相位噪声。 两个LC坦克被嵌套和切换。 通过调节不活动的水箱，可以增加活动水箱的范围，并可以进行更精细的调节。

公开(公告)号：US08704566B2

公开(公告)日：2014-04-22

申请号：US13608277

申请日：2012-09-10

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/06

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

摘要翻译： 提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。 可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。 可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。 可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

公开(公告)号：US20140070856A1

公开(公告)日：2014-03-13

申请号：US13611008

申请日：2012-09-12

申请人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

发明人： Herschel A. Ainspan ,  Mark A. Ferriss ,  Daniel J. Friedman ,  Alexander V. Rylyakov ,  Jose A. Tierno

IPC分类号： H03L7/107

CPC分类号： H03L7/1072 ,  H03L7/087 ,  H03L7/089 ,  H03L7/093

摘要： Phase locked loop (PLL) architectures are provided such as hybrid PLL architectures having separate digital integrating control paths and analog proportional control paths. An analog proportional control path can be implemented with a charge pump circuit that includes resistors in series with CMOS switches to generate control currents (e.g., Up/Down control currents) which are used to adjust a control voltage applied to a digitally controlled oscillator. A digital integrating control path can be implemented with a series of sigma-delta modulators that operate at different frequencies to convert higher bit data signals to lower bit data signals along the digital integrating control path. A single phase frequency detector may be implemented to generate control signals that separately control the analog proportional and digital integrating control paths.

摘要翻译： 提供了锁相环（PLL）架构，例如具有单独的数字积分控制路径和模拟比例控制路径的混合PLL架构。 可以使用包括与CMOS开关串联的电阻器的电荷泵电路来实现模拟比例控制路径，以产生用于调节施加到数字控制振荡器的控制电压的控制电流（例如，上/下控制电流）。 可以用一系列在不同频率下操作的Σ-Δ调制器来实现数字积分控制路径，以将较高位数据信号转换为沿着数字积分控制路径的较低位数据信号。 可以实现单相频率检测器来产生分别控制模拟比例和数字积分控制路径的控制信号。

公开(公告)号：US20120317062A1

公开(公告)日：2012-12-13

申请号：US13587594

申请日：2012-08-16

申请人： Bernard V. BREZZO ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

发明人： Bernard V. BREZZO ,  Leland Chang ,  Steven K. Esser ,  Daniel J. Friedman ,  Yong Liu ,  Dharmendra S. Modha ,  Robert K. Montoye ,  Bipin Rajendran ,  Jae-sun Seo ,  Jose A. Tierno

IPC分类号： G06N3/08

CPC分类号： G06N3/063 ,  G06N3/04 ,  G06N3/049 ,  G06N3/082

摘要： A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.

摘要翻译： 提供可重构神经网络电路。 可重构神经网络电路包括电子突触阵列，其包括互连多个数字电子神经元的多个突触。 每个神经元包括积分器，其对输入尖峰进行积分，并且当集成输入超过阈值时产生信号。 电路还包括用于重新配置突触阵列的控制模块。 控制模块包括控制电路操作的定时的全局最终状态机，以及允许加标神经元依次访问突触阵列的优先编码器。

公开(公告)号：US20120084241A1

公开(公告)日：2012-04-05

申请号：US12895791

申请日：2010-09-30

申请人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

发明人： Daniel J. Friedman ,  Seongwon Kim ,  Chung H. Lam ,  Dharmendra S. Modha ,  Bipin Rajendran ,  Jose A. Tierno

IPC分类号： G06N3/063

CPC分类号： G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G11C11/54 ,  G11C13/0004

摘要： Embodiments of the invention relate to a neuromorphic network for producing spike-timing dependent plasticity. The neuromorphic network includes a plurality of electronic neurons and an interconnect circuit coupled for interconnecting the plurality of electronic neurons. The interconnect circuit includes plural synaptic devices for interconnecting the electronic neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

摘要翻译： 本发明的实施例涉及一种用于产生尖峰时序相关可塑性的神经形态网络。 神经元网络包括多个电子神经元和耦合用于互连多个电子神经元的互连电路。 互连电路包括用于经由轴突路径，枝晶路径和膜路径互连电子神经元的多个突触装置。 每个突触装置包括可变状态电阻器和具有栅极端子，源极端子和漏极端子的晶体管器件，其中漏极端子与可变状态电阻器的第一端子串联连接。 晶体管器件的源极端子连接到轴突路径，晶体管器件的栅极端子连接到膜路径，并且可变状态电阻器的第二端子连接到树突路径，使得每个突触器件被耦合 在第一轴突路径和第一枝晶路径之间以及在第一膜路径和所述第一枝晶路径之间。

公开(公告)号：US08085841B2

公开(公告)日：2011-12-27

申请号：US12061268

申请日：2008-04-02

申请人： John F. Bulzacchelli ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Alexander V. Rylyakov

发明人： John F. Bulzacchelli ,  Timothy O. Dickson ,  Daniel J. Friedman ,  Alexander V. Rylyakov

IPC分类号： H04L27/01

CPC分类号： H04L25/03019 ,  H04L25/03031

摘要： A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.

摘要翻译： 一种判决反馈均衡器（DFE）和方法，包括耦合到输入端并包括采样保持元件的分支，所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。 电流积分加法器与采样保持元件的输出耦合。 夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。 至少一个先前的决定和输入样本被集成到节点上，其中输入样本在积分期间保持不变，从而减轻输入转换对夏季输出的影响。

公开(公告)号：US20110278155A1

公开(公告)日：2011-11-17

申请号：US12779318

申请日：2010-05-13

申请人： Daniel J. Friedman ,  James R. Kozloski ,  Charles C. Peck, III ,  Stanislav V. Plonsky ,  Ajay K. Royyuru

发明人： Daniel J. Friedman ,  James R. Kozloski ,  Charles C. Peck, III ,  Stanislav V. Plonsky ,  Ajay K. Royyuru

IPC分类号： B01J19/08 ,  H05F3/00

CPC分类号： B82Y15/00 ,  B82B1/003

摘要： Methods for controlling catalysis of a chemical reaction generally includes electrostatically controlling position of a first linear single-molecule polymer inside at least one nanopore fluidly coupled to a reaction chamber comprising a reaction medium and at least one reactant, wherein the first linear single-molecule polymer is coupled to a first catalyst at one end and includes one or more charged sub-units; and creating an electrostatic potential well inside the nanopore, wherein the electrostatic potential well controls a position of the first linear single-molecule polymer inside the at least one nanopore. Also disclosed are apparatuses for controlling catalysis of the chemical reaction.

摘要翻译： 用于控制化学反应催化的方法通常包括静电控制在与包含反应介质和至少一种反应物的反应室流体耦合的至少一个纳米孔内的第一线性单分子聚合物的位置，其中第一线性单分子聚合物 在一端耦合到第一催化剂并且包括一个或多个带电子单元; 以及在所述纳米孔内产生静电势阱，其中所述静电势井控制所述至少一个纳米孔内的所述第一线性单分子聚合物的位置。 还公开了用于控制化学反应的催化的装置。