摘要:
A method and apparatus for using weighted random patterns in a partial scan test. A computer generates deterministic patterns on the partial scan design. Deterministic patterns that have the same number of capture clocks between adjacent scan loads are grouped together into pattern groups. A computer then determines a set of weights corresponding to each of the pattern groups. A tester then uses these weights as a filter to weighted random test patterns and applies these filtered weighted random test patterns along with the appropriate number of capture clock pulses to a device under test.
摘要:
An update mechanism and approach are provided for configuring a communications receiver. According to the approach, a time domain equalizer and a frequency domain equalizer in a communications receiver are dynamically updated based upon performance data that indicates the performance of a communications channel from which the communications receiver receives data. This approach accounts for changes in the communications channel attributable to changes in the transmission medium or changes in interference sources.
摘要:
MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.
摘要:
A device has a processor for processing a vertex processing stage, a sub-screen dividing stage and a pixel rendering stage of a three-dimensional (3D) graphics pipeline. The processor includes processing threads which balance the work load of the 3D graphics pipeline by prioritizing processing for the pixel rendering stage over other stages. Each processing thread, operating in parallel and independently, checks a level of tasks in a Task list of sub-screen tasks. If the level is below a threshold value, empty or the sub-screen tasks are all locked, the processing thread loops to the vertex processing stage. Otherwise, the processing thread processes a sub-screen task during the pixel rendering stage.
摘要:
An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.
摘要:
Aspects of a method and system for an asynchronous pipeline architecture for multiple independent dual/stereo channel PCM processing are provided. Asynchronously pipeline processing of audio information comprised within a decoded PCM frame may be based on metadata information generated from the decoded PCM frame and an output decoding rate. The asynchronously pipeline processing may comprise mixing a primary audio information portion and a secondary audio information, portion, sample rate converting the audio information, and buffering the audio information. The asynchronously pipeline processing may comprise multiple pipeline stages. Feeding back an output of one of the pipeline stages to an input of a previous one of the pipeline stages may be enabled. The metadata information may comprise a frame start indicator associated with the decoded PCM frame and/or a plurality of mixing coefficients.
摘要:
In one embodiment, there is presented an integrated circuit. The integrated circuit comprises a transport processor and a host processor. The transport processor parses a media stream. The host processor determines whether a media stream is Blu-ray or HD-DVD and configures the transport processor based on whether the media stream is Blu-ray or HD-DVD.
摘要:
A test structure and methods of using and making the same are provided. In one aspect, a test structure is provided that includes a first conductor that has a first end and a second conductor that has a second end positioned above the first end. A third conductor is positioned between the first end of the first conductor and the second end of the second conductor. A first electrode is coupled to the first conductor at a first distance from the third conductor and a second electrode coupled to the first conductor at a second distance from the third conductor. A third electrode is coupled to the second conductor at a third distance from the third conductor and a fourth electrode is coupled to the second conductor at a fourth distance from the third conductor. The first through fourth electrodes provide voltage sense taps and the first and second conductors provide current sense taps from which the resistance of the third conductor may be derived.
摘要:
The present invention relates to application of compounds of formula (1) (Gibberellins) and their derivatives for the preparation of a pharmaceutical composition or medicaments for the treatment of diabetes, its complications and associated conditions, including obesity, micro and macro vascular diseases, nephropathy, neuropathy, eye diseases, diabetic ulcerations and the like. The method results the normalization of serum glucose level and other physiological conditions.
摘要:
A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.