公开(公告)号：US20160093349A1

公开(公告)日：2016-03-31

申请号：US14502367

申请日：2014-09-30

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Dimitri Houssameddine ,  Syed M. Alam ,  Jon Slaughter ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

Abstract translation: 存储器设备被配置为识别要从第一状态改变到第二状态的位单元的集合。 在一些示例中，存储器件可以向该位单元集合施加第一电压以将位组中的至少第一部分改变为第二状态。 在一些情况下，存储器件还可以识别在应用第一电压之后保持在第一状态的位单元的第二部分。 在这些情况下，存储器件可以将具有更大幅度，持续时间或两者的第二电压施加到位单元集合的第二部分，以便将位单元的第二部分设置为第二状态。

公开(公告)号：US09293698B2

公开(公告)日：2016-03-22

申请号：US14701831

申请日：2015-05-01

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  B82Y10/00

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: In one aspect, the present inventions are directed to a magnetoresistive structure having a tunnel junction, and a process for manufacturing such a structure. The tunnel barrier may be formed between a free layer and a fixed layer in a plurality of repeating process of depositing a metal material and oxidizing at least a portion of the metal material. Where the tunnel barrier is formed by deposition of at least three metal materials interceded by an associated oxidization thereof, the oxidation dose associated with the second metal material may be greater than the oxidation doses associated with the first and third metal materials. In certain embodiments, the fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.

Abstract translation: 一方面，本发明涉及具有隧道结的磁阻结构，以及制造这种结构的方法。 可以在沉积金属材料和氧化至少一部分金属材料的多个重复工艺中，在自由层和固定层之间形成隧道势垒。 在通过沉积由其相关氧化作用介入的至少三种金属材料形成隧道势垒的地方，与第二金属材料相关的氧化剂量可能大于与第一和第三金属材料相关联的氧化剂量。 在某些实施例中，固定层可以在两层铁磁材料之间的固定层中包括不连续的金属层，例如Ta。

公开(公告)号：US20160055894A1

公开(公告)日：2016-02-25

申请号：US14697577

申请日：2015-04-27

Applicant: Everspin Technologies, Inc.

Inventor： Dimitri Houssameddine ,  Jon Slaughter

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C11/1697 ,  G11C29/70 ,  G11C29/74 ,  G11C29/838 ,  G11C2213/78 ,  G11C2213/79

Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.

Abstract translation: 自旋扭矩磁随机存取存储器（MRAM）中的存储单元包括每个存储器单元内的至少两个磁性隧道结，其中每个存储器单元仅存储单个数据位的信息。 耦合到存储器单元的访问电路即使当存储单元内的磁隧道结之一有缺陷并且不再起作用时，也能够读取和写入存储单元。 自参考和参考读取可以与多个磁性隧道结存储器单元结合使用。 在一些实施例中，向存储器单元的写入迫使所有磁隧道结进入已知状态，而在其它实施例中，磁性隧道结的子集被强制为已知状态。

公开(公告)号：US20160013401A1

公开(公告)日：2016-01-14

申请号：US14860657

申请日：2015-09-21

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive memory element (for example, a spin-torque magnetoresistive memory element), includes first and second dielectric layers, wherein at least one of the dielectric layers is a magnetic tunnel junction. The memory element also includes a free magnetic layer having a first surface in contact with the first dielectric layer and a second surface in contact with the second dielectric layer. The free magnetic layer, which is disposed between the first and second dielectric layers, includes (i) a first high-iron interface region located along the first surface of the free magnetic layer, wherein the first high-iron interface region has at least 50% iron by atomic composition, and (ii) a first layer of ferromagnetic material adjacent to the first high-iron interface region, the first high-iron interface region between the first layer of ferromagnetic material and the first surface of the free magnetic layer.

Abstract translation: 磁阻存储元件（例如，自旋扭矩磁阻存储元件）包括第一和第二电介质层，其中至少一个电介质层是磁性隧道结。 存储元件还包括具有与第一介电层接触的第一表面和与第二介电层接触的第二表面的自由磁性层。 设置在第一和第二电介质层之间的自由磁性层包括（i）沿着自由磁性层的第一表面设置的第一高铁界面区域，其中第一高铁界面区域具有至少50 以及（ii）与第一高铁界面区域相邻的第一铁磁材料层，第一铁磁材料层与自由磁性层的第一表面之间的第一高铁界面区域。

公开(公告)号：US09136464B1

公开(公告)日：2015-09-15

申请号：US14037087

申请日：2013-09-25

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jason Janesky ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/02 ,  B82Y10/00

CPC classification number: H01L43/02 ,  B82Y10/00 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  Y10S977/935

Abstract: An MRAM device, and a process for manufacturing the device, provides improved breakdown distributions, a reduced number of bits with a low breakdown voltage, and an increased MR, thereby improving reliability, manufacturability, and error-free operation. A tunnel barrier is formed between a free layer and a fixed layer in three repeating steps of forming a metal material, interceded by oxidizing each of the metal materials. The oxidization of the third metal material is greater than the dose of the first metal, but less than the dose of the second metal. The fixed layer may include a discontinuous layer of a metal, for example, Ta, in the fixed layer between two layers of a ferromagnetic material.

Abstract translation: MRAM器件以及用于制造器件的工艺提供了改进的击穿分布，具有低击穿电压的位数减少以及增加的MR，从而提高了可靠性，可制造性和无错误操作。 在自由层和固定层之间形成隧道势垒，在三个重复步骤中形成金属材料，通过氧化每种金属材料进行交换。 第三金属材料的氧化大于第一金属的剂量，但小于第二金属的剂量。 固定层可以在两层铁磁材料之间的固定层中包括不连续的金属层，例如Ta。

公开(公告)号：US20140159179A1

公开(公告)日：2014-06-12

申请号：US14168095

申请日：2014-01-30

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Jijun Sun ,  Phillip Mather ,  Srinivas Pietambaram ,  Jon Slaughter ,  Renu Whig ,  Nicholas Rizzo

IPC: H01L43/10 ,  H01L43/12

CPC classification number: H01L43/10 ,  G01R33/098 ,  H01L43/12 ,  Y10T29/49117

Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.

Abstract translation: 提供传感器和制造工艺，用于形成具有基本上正交的磁化方向的参考层，具有零偏移并具有小的补偿角。 示例性实施例包括基于磁阻薄膜的磁场传感器的传感器层堆叠，传感器层堆叠包括钉扎层; 包括在钉扎层上的无定形材料层的钉扎层和在非晶材料层上的第一层结晶材料; 在被钉扎层上的非磁性耦合层; 在非磁耦合层上的固定层; 固定层上的隧道势垒; 以及在非磁性中间层上的感测层。 另一个实施例包括传感器层堆叠，其中包括由非晶层隔开的两个结晶层的钉扎层。

公开(公告)号：US20140138346A1

公开(公告)日：2014-05-22

申请号：US13972637

申请日：2013-08-21

Applicant: EverSpin Technologies, Inc.

Inventor： Renu Whig ,  Philip Mather ,  Kenneth Smith ,  Sanjeev Aggarwal ,  Jon Slaughter ,  Nicholas Rizzo

IPC: H01L43/12 ,  G01R33/09

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。

公开(公告)号：US08647891B2

公开(公告)日：2014-02-11

申请号：US13909622

申请日：2013-06-04

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Phillip Mather ,  Srinivas Pietambaram ,  Jon Slaughter ,  Renu Whig ,  Nicholas Rizzo

IPC: H01L21/00

CPC classification number: H01L43/10 ,  G01R33/098 ,  H01L43/12 ,  Y10T29/49117

Abstract: A sensor and fabrication process are provided for forming reference layers with substantially orthogonal magnetization directions having zero offset with a small compensation angle. An exemplary embodiment includes a sensor layer stack of a magnetoresistive thin-film based magnetic field sensor, the sensor layer stack comprising a pinning layer; a pinned layer including a layer of amorphous material over the pinning layer, and a first layer of crystalline material over the layer of amorphous material; a nonmagnetic coupling layer over the pinned layer; a fixed layer over the nonmagnetic coupling layer; a tunnel barrier over the fixed layer; and a sense layer over the nonmagnetic intermediate layer. Another embodiment includes a sensor layer stack where a pinned layer including two crystalline layers separated by a amorphous layer.

Abstract translation: 提供传感器和制造工艺，用于形成具有基本上正交的磁化方向的参考层，具有零偏移并具有小的补偿角。 示例性实施例包括基于磁阻薄膜的磁场传感器的传感器层堆叠，传感器层堆叠包括钉扎层; 包括在钉扎层上的无定形材料层的钉扎层和在非晶材料层上的第一层结晶材料; 在被钉扎层上的非磁性耦合层; 在非磁耦合层上的固定层; 固定层上的隧道势垒; 以及在非磁性中间层上的感测层。 另一个实施例包括传感器层堆叠，其中包括由非晶层隔开的两个结晶层的钉扎层。

公开(公告)号：US10535390B2

公开(公告)日：2020-01-14

申请号：US15831736

申请日：2017-12-05

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Sanjeev Aggarwal ,  Sarin A. Deshpande ,  Jon Slaughter

IPC: H01L29/82 ,  H01L21/8246 ,  H01L29/06 ,  H01L43/12 ,  H01L27/22 ,  B44C1/22 ,  G11B5/127 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

Abstract: The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.

公开(公告)号：US10516103B1

公开(公告)日：2019-12-24

申请号：US16551952

申请日：2019-08-27

Applicant: Everspin Technologies, Inc.

Inventor： Renu Whig ,  Jijun Sun ,  Nicholas Rizzo ,  Jon Slaughter ,  Dimitri Houssameddine ,  Frederick Mancoff

IPC: H01L21/00 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.