公开(公告)号：US08432030B2

公开(公告)日：2013-04-30

申请号：US13171788

申请日：2011-06-29

Applicant: Rajesh Kumar Malhan ,  C Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

Inventor： Rajesh Kumar Malhan ,  C Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

IPC: H01L23/48

CPC classification number: H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US08304316B2

公开(公告)日：2012-11-06

申请号：US11961410

申请日：2007-12-20

Applicant: Florin Udrea ,  Gehan Anil Joseph Amaratunga ,  Tanya Trajkovic ,  Vasantha Pathirana

Inventor： Florin Udrea ,  Gehan Anil Joseph Amaratunga ,  Tanya Trajkovic ,  Vasantha Pathirana

IPC: H01L21/336

CPC classification number: H01L29/0657 ,  H01L21/8249 ,  H01L22/26 ,  H01L29/063 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/7393 ,  H01L29/7816

Abstract: In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

Abstract translation: 在功率半导体器件和形成功率半导体器件的方法中，将半导体衬底的薄层留在半导体器件的漂移区域的下方。 功率半导体器件具有包括漂移区的有源区，并且具有形成在设置在半导体衬底上的层中的顶表面和底表面。 在有源区下面的半导体衬底的一部分被去除以在漂移区下方留下半导体衬底的薄层。 电端子直接或间接提供到有源区的顶表面，以允许电压横向跨越漂移区域施加。

公开(公告)号：US08174069B2

公开(公告)日：2012-05-08

申请号：US12186231

申请日：2008-08-05

Applicant: Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

Inventor： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

IPC: H01L29/94

CPC classification number: H01L29/0847 ,  H01L29/0657 ,  H01L29/0839 ,  H01L29/0856 ,  H01L29/0878 ,  H01L29/4232 ,  H01L29/42372 ,  H01L29/7394 ,  H01L29/7824

Abstract: A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

Abstract translation: 功率半导体器件具有顶表面和相对的底表面，其下面的一部分是半导体衬底的厚部分。 装置的漂移区域的至少一部分具有没有或仅有半导体衬底的薄的部分位于其下方。 顶表面具有高电压端子和与其连接的低电压端子，以允许跨越漂移区域横向施加电压。 在顶表面上设置至少两个MOS（金属氧化物半导体）栅极。 器件在其顶表面处具有至少一个相对高度掺杂的区域，其在所述第一和第二MOS栅极之间延伸并与之接触。 该器件具有改进的防止寄生晶体管触发或闩锁的保护，而不会导致导通电压降或开关速度受损。

公开(公告)号：US07968940B2

公开(公告)日：2011-06-28

申请号：US11863231

申请日：2007-09-27

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/66

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/66348 ,  H01L29/7396

Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n− drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

Abstract translation: 具有两个栅极的双栅极IGBT指的是其中第二栅极用于控制空穴电流的阴极。 在导通状态下，可以大大抑制空穴电流。 在切换期间，允许空穴电流流过第二通道。 结合具有预形成的空穴通道的耗尽型p沟道MOSFET，当0V或者低于特定阈值电压的正电压被施加在第二栅极和阴极之间时，其导通的电压不被用于p沟道栅极的负电压 。 通过增加n阱的掺杂和宽度降低碱运输因子，或者通过减少深阱的掺杂降低注入效率，提供通过积极收集的空穴量的主动控制。 器件至少包括阳极，阴极，半导体衬底，n-漂移区，第一和第二栅极，n +阴极区域; p +阴极短，深p阱，n阱和预形成的孔道。

公开(公告)号：US07849727B2

公开(公告)日：2010-12-14

申请号：US12065296

申请日：2006-07-12

Applicant: Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

Inventor： Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

IPC: G01N7/00

CPC classification number: G01N33/0047 ,  G01N27/14 ,  G01N33/0031

Abstract: A gas-sensing semiconductor device 1′ is fabricated on a silicon substrate 2′ having a thin silicon dioxide insulating layer 3′ in which a resistive heater 6 made of doped single crystal silicon formed simultaneously with source and drain regions of CMOS circuitry is embedded. The device 1′ includes a sensing area provided with a gas-sensitive layer 9′ separated from the heater 6′ by an insulating layer 4′. As one of the final fabrication steps, the substrate 2′ is back-etched so as to form a thin membrane in the sensing area. The heater 6′ has a generally circular-shaped structure surrounding a heat spreading plate 16′, and consists of two sets 20′, 21′ of meandering resistors having arcuate portions nested within one another and interconnected in labyrinthine form. The fabrication of the heater at the same time as the source and drain regions of CMOS circuitry is particularly advantageous in that the gas-sensing semiconductor device is produced without requiring any fabrication steps in addition to those already employed in the IC processing apart from a post-CMOS back etch and deposition of the gas-sensitive layer. The circular design is advantageous in that it is the best solution to minimise the size of the membrane at fixed power loss and heated area.

Abstract translation: 在具有薄的二氧化硅绝缘层3'的硅衬底2'上制造气体感测半导体器件1'，其中嵌入与CMOS电路的源极和漏极区域同时形成的由掺杂单晶硅制成的电阻加热器6。 装置1'包括具有通过绝缘层4'与加热器6'分离的气敏层9'的感测区域。 作为最终制造步骤之一，衬底2'被反蚀刻以在感测区域中形成薄膜。 加热器6'具有围绕散热板16'的大致圆形结构，并且由具有彼此嵌套并且以迷宫形式互连的弓形部分的曲折电阻器的两组20'，21'组成。 与CMOS电路的源极和漏极区域同时地制造加热器是特别有利的，因为除了在后处理中已经用于IC处理中的那些之外，制造气体感测半导体器件不需要任何制造步骤 -CMOS背蚀刻和气敏层的沉积。 圆形设计是有利的，因为它是在固定功率损耗和加热面积下最小化膜尺寸的最佳解决方案。

公开(公告)号：US20100283514A1

公开(公告)日：2010-11-11

申请号：US12677131

申请日：2008-08-28

Applicant: Akitaka Soeno ,  Jun Saito ,  Gehan Anil Joseph Amaratunga ,  Florin Udrea

Inventor： Akitaka Soeno ,  Jun Saito ,  Gehan Anil Joseph Amaratunga ,  Florin Udrea

IPC: G05F3/02

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H03K17/08128 ,  H03K17/0828

Abstract: In a reverse conducting semiconductor device, which forms a composition circuit, a positive voltage that is higher than a positive voltage of a collector electrode may be applied to an emitter electrode. In this case, in a region of the reverse conducting semiconductor device in which a return diode is formed, a body contact region functions as an anode, a drift contact region functions as a cathode, and current flows from the anode to the cathode. When a voltage having a lower electric potential than the collector electrode is applied to the trench gate electrode at that time, p-type carriers are generated within the cathode and a quantity of carriers increases within the return diode. As a result, a forward voltage drop of the return diode lowers, and constant loss of electric power can be reduced. Electric power loss can be reduced in a power supply device that uses such a composition circuit in which a switching element and the return diode are connected in reverse parallel.

Abstract translation: 在形成合成电路的反向导通半导体器件中，可以将高于集电极的正电压的正电压施加到发射极。 在这种情况下，在形成有返回二极管的反向导通半导体器件的区域中，体接触区域用作阳极，漂移接触区域用作阴极，并且电流从阳极流到阴极。 此时当沟槽栅电极施加具有比集电极电位低的电压的电压时，在阴极内产生p型载流子，在返回二极管内增加载流子数量。 结果，返回二极管的正向压降降低，并且可以减少电力的恒定损失。 在使用其中开关元件和返回二极管反向并联连接的组合电路的电源装置中，电力损耗可以减小。

公开(公告)号：US20090126460A1

公开(公告)日：2009-05-21

申请号：US12065296

申请日：2006-07-12

Applicant: Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

Inventor： Julian William Gardner ,  Florin Udrea ,  Takao Iwaki ,  James Anthony Covington

IPC: G01N7/00 ,  H01L29/78

CPC classification number: G01N33/0047 ,  G01N27/14 ,  G01N33/0031

Abstract: A gas-sensing semiconductor device 1′ is fabricated on a silicon substrate 2′ having a thin silicon dioxide insulating layer 3′ in which a resistive heater 6 made of doped single crystal silicon formed simultaneously with source and drain regions of CMOS circuitry is embedded. The device 1′ includes a sensing area provided with a gas-sensitive layer 9′ separated from the heater 6′ by an insulating layer 4′. As one of the final fabrication steps, the substrate 2′ is back-etched so as to form a thin membrane in the sensing area. The heater 6′ has a generally circular-shaped structure surrounding a heat spreading plate 16′, and consists of two sets 20′, 21′ of meandering resistors having arcuate portions nested within one another and interconnected in labyrinthine form. The fabrication of the heater at the same time as the source and drain regions of CMOS circuitry is particularly advantageous in that the gas-sensing semiconductor device is produced without requiring any fabrication steps in addition to those already employed in the IC processing apart from a post-CMOS back etch and deposition of the gas-sensitive layer. The circular design is advantageous in that it is the best solution to minimise the size of the membrane at fixed power loss and heated area.

Abstract translation: 在具有薄的二氧化硅绝缘层3'的硅衬底2'上制造气体感测半导体器件1'，其中嵌入与CMOS电路的源极和漏极区域同时形成的由掺杂单晶硅制成的电阻加热器6。 装置1'包括具有通过绝缘层4'与加热器6'分离的气敏层9'的感测区域。 作为最终制造步骤之一，衬底2'被反蚀刻以在感测区域中形成薄膜。 加热器6'具有围绕散热板16'的大致圆形结构，并且由具有彼此嵌套并且以迷宫形式互连的弓形部分的曲折电阻器的两组20'，21'组成。 与CMOS电路的源极和漏极区域同时地制造加热器是特别有利的，因为除了在后处理中已经用于IC处理中的那些之外，制造气体感测半导体器件不需要任何制造步骤 -CMOS背蚀刻和气敏层的沉积。 圆形设计是有利的，因为它是在固定功率损耗和加热面积下最小化膜尺寸的最佳解决方案。

公开(公告)号：US07495300B2

公开(公告)日：2009-02-24

申请号：US11092654

申请日：2005-03-30

Applicant: Julian William Gardner ,  James Anthony Covington ,  Florin Udrea

Inventor： Julian William Gardner ,  James Anthony Covington ,  Florin Udrea

IPC: H01L29/78

CPC classification number: G01N27/128

Abstract: A gas-sensing semiconductor device is fabricated on a silicon substrate having a thin silicon oxide insulating layer in which a resistive heater made of a CMOS compatible high temperature metal is embedded. The high temperature metal is tungsten. The device includes at least one sensing area provided with a gas-sensitive layer separated from the heater by an insulating layer. As one of the final fabrication steps, the substrate is back-etched so as to form a thin membrane in the sensing area. Except for the back-etch and the gas-sensitive layer formation, that are carried out post-CMOS, all other layers, including the tungsten resistive heater, are made using a CMOS process employing tungsten metallisation. The device can be monolithically integrated with the drive, control and transducing circuitry using low cost CMOS processing. The heater, the insulating layer and other layers are made within the CMOS sequence and they do not require extra masks or processing.

Abstract translation: 气体感测半导体器件制造在具有薄的氧化硅绝缘层的硅衬底上，其中嵌入由CMOS兼容的高温金属制成的电阻加热器。 高温金属是钨。 该装置包括设置有通过绝缘层与加热器分离的气敏层的至少一个感测区域。 作为最终制造步骤之一，衬底被反蚀刻以在感测区域中形成薄膜。 除了在CMOS之后执行的背蚀刻和气敏层形成之外，包括钨电阻加热器在内的所有其它层均采用采用钨金属化的CMOS工艺制成。 该器件可以使用低成本CMOS处理与驱动器，控制和转换电路单片集成。 加热器，绝缘层和其他层是在CMOS序列内制成的，它们不需要额外的掩模或处理。

公开(公告)号：US07411272B2

公开(公告)日：2008-08-12

申请号：US11174605

申请日：2005-07-06

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L29/00

CPC classification number: H01L29/7816 ,  H01L21/76289 ,  H01L21/764 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/083 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region. In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface and at least one electrical terminal is connected directly or indirectly to the bottom surface to allow a voltage to be applied vertically across the drift region. In each of these embodiments, the bottom surface of the membrane does not have a semiconductor substrate positioned adjacent thereto.

Abstract translation: 功率半导体器件具有包括漂移区域的有源区域。 漂移区域的至少一部分设置在具有相对的顶表面和底表面的膜中。 在一个实施例中，膜的顶表面具有直接或间接连接到其上的电端子，以允许跨越漂移区横向施加电压。 在另一个实施例中，至少一个电端子直接或间接地连接到顶表面，并且至少一个电端子直接或间接地连接到底表面，以允许垂直地跨越漂移区域施加电压。 在这些实施例的每一个中，膜的底表面不具有与其相邻定位的半导体衬底。

公开(公告)号：US20060049406A1

公开(公告)日：2006-03-09

申请号：US10936721

申请日：2004-09-09

Applicant: Gehan Amaratunga ,  Florin Udrea

Inventor： Gehan Amaratunga ,  Florin Udrea

IPC: H01L29/76

CPC classification number: H01L29/7824 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/78603 ,  H01L29/78624

Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.