公开(公告)号：US09831131B1

公开(公告)日：2017-11-28

申请号：US15279732

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. Jacob

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.

公开(公告)号：US09564447B1

公开(公告)日：2017-02-07

申请号：US14842345

申请日：2015-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Ajey P. Jacob ,  Min-hwa Chi

IPC: H01L27/112 ,  G11C13/00

CPC classification number: H01L27/11206 ,  G11C13/0002 ,  G11C13/0009 ,  G11C13/0069 ,  G11C13/025 ,  G11C2013/008 ,  H01L23/5256 ,  H01L23/53276 ,  H01L27/112 ,  H01L29/0676 ,  H01L29/413

Abstract: Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.

Abstract translation: 提供了可编程器件制造的方法和结构。 制造可编程装置的方法包括例如在可编程装置的层中形成至少一个通孔，并在至少一个通孔开口的下表面上提供催化材料; 在所述至少一个通孔开口中使用所述催化材料形成多个纳米线或纳米管作为用于形成所述多个纳米线或纳米管的催化剂; 以及在所述至少一个通孔开口中提供介电材料，使得所述电介质材料包围所述多个纳米线或纳米管。 可编程设备在随后或单独的编程步骤中可以通过介电材料和多个纳米线或纳米管的热氧化使可编程器件的编程永久化，在至少一个通孔开口之后留下非导电材料。

公开(公告)号：US20160284802A1

公开(公告)日：2016-09-29

申请号：US15176073

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Murat K. Akarvardar ,  Ajey P. Jacob

IPC: H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76216 ,  H01L21/76281 ,  H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

公开(公告)号：US20160035863A1

公开(公告)日：2016-02-04

申请号：US14883049

申请日：2015-10-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: An illustrative method includes forming a FinFET device above structure comprising a semiconductor substrate, a first epi semiconductor material and a second epi semiconductor material that includes forming an initial fin structure that comprises portions of the semiconductor substrate, the first epi material and the second epi material, recessing a layer of insulating material such that a portion, but not all, of the second epi material portion of the initial fin structure is exposed so as to define a final fin structure, forming a gate structure above and around the final fin structure, removing the first epi material of the initial fin structure and thereby define an under-fin cavity under the final fin structure and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 一种说明性的方法包括在包括半导体衬底，第一外延半导体材料和第二外延半导体材料的结构之上形成FinFET器件，其包括形成包括半导体衬底，第一外延材料和第二外延材料的部分的初始鳍结构 使一层绝缘材料凹陷，使得初始翅片结构的第二外延材料部分的一部分（但不是全部）暴露以便限定最终的翅片结构，在最后的翅片结构的上方和周围形成栅极结构， 去除初始翅片结构的第一外延材料，从而在最终翅片结构下限定底鳍腔，并用应力材料基本上填充底鳍腔。

公开(公告)号：US20160013296A1

公开(公告)日：2016-01-14

申请号：US14860276

申请日：2015-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

Abstract translation: 本文公开的一个示例性器件包括形成在由第一半导体材料构成的衬底中的衬底鳍片，其中衬底鳍片的至少一个侧壁基本上位于衬底的晶体结构的<100>晶体方向上，替换鳍片 位于所述衬底翅片上方的结构，其中所述替换翅片结构由与所述第一半导体材料不同的半导体材料和位于所述替换翅片结构的至少一部分周围的栅极结构构成。

公开(公告)号：US20150325436A1

公开(公告)日：2015-11-12

申请号：US14274406

申请日：2014-05-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Steven Bentley ,  Ajey P. Jacob

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L21/02538 ,  H01L29/20 ,  H01L29/66 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices including a fin and method of forming the semiconductor devices are provided herein. In an embodiment, a method of forming a semiconductor device includes forming a fin overlying a semiconductor substrate. The fin is formed by epitaxially-growing a semiconductor material over the semiconductor substrate, and the fin has a first portion that is proximal to the semiconductor substrate and a second portion that is spaced from the semiconductor substrate by the first portion. A gate structure is formed over the fin and the semiconductor substrate. The first portion of the fin is etched to form a gap between the second portion and the semiconductor substrate.

Abstract translation: 本文提供了包括翅片的半导体器件和形成半导体器件的方法。 在一个实施例中，形成半导体器件的方法包括形成覆盖半导体衬底的散热片。 鳍状物通过在半导体衬底上外延生长半导体材料而形成，并且鳍具有靠近半导体衬底的第一部分和通过第一部分与半导体衬底间隔开的第二部分。 在鳍片和半导体衬底上形成栅极结构。 蚀刻鳍的第一部分以在第二部分和半导体衬底之间形成间隙。

公开(公告)号：US08853019B1

公开(公告)日：2014-10-07

申请号：US13798616

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Jeremy A. Wahl ,  Kerem Akarvardar ,  Ajey P. Jacob ,  Daniel T. Pham

IPC: H01L29/94 ,  H01L29/66 ,  B82Y40/00

CPC classification number: H01L29/42392 ,  B82Y40/00 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成具有至少30％的锗浓度的硅/锗层，形成多个间隔开的沟槽，其延伸穿过硅/锗层并且至少部分地进入半导体 衬底，其中所述沟槽限定由所述衬底的一部分和所述硅/锗层的一部分组成的器件的鳍结构，所述硅/锗层的所述部分具有第一横截面构造，形成层 的绝缘材料在沟槽中并在鳍结构之上，对器件进行退火处理，以使硅/锗层的第一截面构型变为不同于第二截面结构 第一横截面构造，以及围绕具有第二横截面的硅/锗层的至少一部分形成最终栅极结构 功能配置

公开(公告)号：US20140264488A1

公开(公告)日：2014-09-18

申请号：US13839998

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody Fronheiser ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kerem Akarvardar

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative device disclosed herein includes a substrate fin formed in a substrate comprised of a first semiconductor material, wherein at least a sidewall of the substrate fin is positioned substantially in a crystallographic direction of the crystalline structure of the substrate, a replacement fin structure positioned above the substrate fin, wherein the replacement fin structure is comprised of a semiconductor material that is different from the first semiconductor material, and a gate structure positioned around at least a portion of the replacement fin structure.

Abstract translation: 本文公开的一个示例性器件包括形成在由第一半导体材料构成的衬底中的衬底鳍片，其中衬底鳍片的至少一个侧壁基本上位于衬底的晶体结构的<100>晶体方向上，替换鳍片 位于所述衬底翅片上方的结构，其中所述替换翅片结构由与所述第一半导体材料不同的半导体材料和位于所述替换翅片结构的至少一部分周围的栅极结构构成。