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    UNDOPED EPITAXIAL LAYER FOR JUNCTION ISOLATION IN A FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE
    1.
    发明申请
    UNDOPED EPITAXIAL LAYER FOR JUNCTION ISOLATION IN A FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE 审中-公开
    用于FIN场效应晶体管（FINFET）器件中的连接隔离的未封装外延层

    公开(公告)号：US20150137237A1

    公开(公告)日：2015-05-21

    申请号：US14086199

    申请日：2013-11-21

    Applicant: Globalfoundries Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat K. Akarvardar

    IPC: H01L29/78 ,  H01L29/06 ,  H01L21/761 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L29/0646 ,  H01L29/66795

    Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (FinFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an undoped epitaxial (epi) layer between the embedded S/D and the gate structure. The device may further include an epitaxial (epi) bottom region of the embedded S/D, wherein the epi bottom region is counter doped to a polarity of the embedded S/D, and a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions is doped and the epi bottom region is undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

    Abstract translation: 提供了用于隔离集成电路（IC）器件（例如，鳍式场效应晶体管（FinFET））中的源极和漏极区域的方法。 具体地，FinFET器件包括形成在鳍式衬底上的栅极结构; 栅极结构的有源鳍式沟道下方的隔离氧化物; 形成在栅极结构和隔离氧化物附近的嵌入式源极和漏极（S / D）; 以及嵌入式S / D和栅极结构之间的未掺杂的外延（epi）层。 该器件可以进一步包括嵌入式S / D的外延（epi）底部区域，其中外延底部区域被反掺杂到嵌入式S / D的极性，以及一组注入在epi底部区域下方的注入区域， 其中所述一组注入区域是掺杂的，并且所述外延底部区域是未掺杂的。 在一种方法中，嵌入式S / D包括用于p沟道金属氧化物半导体场效应晶体管（PMOSFET）的P ++掺杂硅锗（SiGe）和用于n沟道金属氧化物半导体场效应晶体管的N ++氮化硅（SiN） 半导体场效应晶体管（NMOSFET）。

    DEVICE ISOLATION IN FINFET CMOS
    2.
    发明申请
    DEVICE ISOLATION IN FINFET CMOS 有权
    FINFET CMOS器件隔离

    公开(公告)号：US20140353801A1

    公开(公告)日：2014-12-04

    申请号：US13906852

    申请日：2013-05-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey P. Jacob ,  Murat K. Akarvardar ,  Steven J. Bentley ,  Toshiharu Nagumo ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz

    IPC: H01L21/761 ,  H01L21/762 ,  H01L29/06

    CPC classification number: H01L21/823821 ,  H01L21/02227 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0646 ,  H01L29/66795 ,  H01L29/7851

    Abstract: Embodiments herein provide approaches for device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of replacement fins is formed over the retrograde doped layer, each of the set of replacement fins comprising a high mobility channel material (e.g., silicon, or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of replacement fins to prevent carrier spill-out to the replacement fins.

    Abstract translation: 本文的实施例提供了在互补金属氧化物鳍片场效应晶体管中的器件隔离的方法。 具体地，半导体器件在衬底上形成有逆向掺杂层以最小化源极到漏极穿通泄漏。 在逆向掺杂层上形成一组替代翅片，该组替换鳍片中的每一个包括高迁移率通道材料（例如，硅或硅 - 锗）。 逆向掺杂层可以使用原位掺杂工艺或反掺杂剂逆向植入来形成。 该装置还可以包括位于逆向掺杂层和该替代翅片组之间的碳衬垫，以防止载体溢出到置换翅片。

    Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device
    8.
    发明授权
    Forming embedded source and drain regions to prevent bottom leakage in a dielectrically isolated fin field effect transistor (FinFET) device 有权
    形成嵌入式源极和漏极区域，以防止介电隔离鳍片场效应晶体管（FinFET）器件中的底部泄漏

    公开(公告)号：US09293587B2

    公开(公告)日：2016-03-22

    申请号：US13948374

    申请日：2013-07-23

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey Poovannummoottil Jacob ,  Murat K. Akarvardar

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

    Abstract: Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (finFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an epitaxial (epi) bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D. The device further includes a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions may be doped and the epi bottom region undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

    Abstract translation: 提供了用于隔离集成电路（IC）器件（例如，鳍式场效应晶体管（finFET））中的源极和漏极区域的方法。 具体地，FinFET器件包括形成在鳍式衬底上的栅极结构; 栅极结构的有源鳍式沟道下方的隔离氧化物; 形成在栅极结构和隔离氧化物附近的嵌入式源极和漏极（S / D）; 和嵌入式S / D的外延（epi）底部区域，外延底部区域计数器掺杂到嵌入式S / D的极性。 该器件还包括一组注入在epi底部区域下方的注入区域，其中该组注入区域可以是掺杂的，而epi底部区域未被掺杂。 在一种方法中，嵌入式S / D包括用于p沟道金属氧化物半导体场效应晶体管（PMOSFET）的P ++掺杂硅锗（SiGe）和用于n沟道金属氧化物半导体场效应晶体管的N ++氮化硅（SiN） 半导体场效应晶体管（NMOSFET）。

    Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide
    9.
    发明授权
    Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide 有权
    具有部分电介质隔离的散装finFET，其特征在于在氧化物下方具有穿通停止层

    公开(公告)号：US09385233B2

    公开(公告)日：2016-07-05

    申请号：US13927698

    申请日：2013-06-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat K. Akarvardar ,  Ajey P. Jacob

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

    CPC classification number: H01L29/1083 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76216 ,  H01L21/76281 ,  H01L27/0255 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

    Abstract translation: 公开了具有部分电介质隔离的散装finFET。 电介质隔离设置在通道下方，并且基本上由通道限定，使得其不横向延伸超过源极和漏极区下方的沟道。 这允许增加与沟道相邻放置的SiGe源极和漏极应力器体积，从而允许更加紧张的通道，这改善了载流子迁移率。 N +掺杂的硅区域设置在电介质隔离的下方，并横向延伸超过沟道并且在应力源和漏极区之下，与P +掺杂的源极和漏极SiGe应力器形成反向偏置的p / n结，以使来自下面的漏电流最小化 绝缘体。

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