公开(公告)号：US06791875B2

公开(公告)日：2004-09-14

申请号：US10189528

申请日：2002-07-08

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C1114

CPC分类号： G11C11/16

摘要： Two complementary bit lines corresponding to a selected column are pulled down to a ground voltage via each of a selected MTJ memory cell and a dummy memory cell and are pulled up to a power supply voltage via a read drive selection gate. A read gate corresponding to the selected column drives the voltages of two complementary read data buses by driving force according to the voltage of corresponding complementary two bit lines, respectively. A data reading circuit executes data reading operation on the basis of a voltage difference between the complementary two read data buses. The power supply voltage is determined in consideration of reliability of a tunneling insulating film of an MTJ memory cell.

摘要翻译： 对应于所选列的两个互补位线通过所选择的MTJ存储器单元和虚设存储单元中的每一个被下拉至接地电压，并经由读驱动选择门被上拉至电源电压。 对应于所选择的列的读取门分别根据对应的互补的两个位线的电压通过驱动力来驱动两个互补读数据总线的电压。 数据读取电路基于互补的两条读取数据总线之间的电压差来执行数据读取操作。 考虑到MTJ存储单元的隧道绝缘膜的可靠性来确定电源电压。

公开(公告)号：US06778430B2

公开(公告)日：2004-08-17

申请号：US09887321

申请日：2001-06-25

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C1114

CPC分类号： H01L27/228 ,  G11C8/08 ,  G11C11/15 ,  G11C11/16

摘要： An MTJ memory cell is independently provided with a write word line and a read word line used for data write and data read. By separately arranging read word lines every two regions formed by dividing a memory array in the column direction, it is possible to reduce signal propagation delays of the read word lines and accelerate the data read operation. Activation of each read word line is controlled by a write word line in accordance with a row selection result in a hierarchical manner. A word-line-current control circuit forms and cuts off the current path of a write word line correspondingly to data write and data read.

摘要翻译： MTJ存储单元独立地具有用于数据写入和数据读取的写字线和读字线。 通过在列方向上划分存储器阵列形成的每两个区域分开布置读取字线，可以减少读取字线的信号传播延迟并加速数据读取操作。 每个读取字线的激活根据分层方式的行选择结果由写入字线控制。 字线电流控制电路对应于数据写入和数据读取形成并切断写入字线的当前路径。

公开(公告)号：US06777986B2

公开(公告)日：2004-08-17

申请号：US10217391

申请日：2002-08-14

申请人： Hideto Hidaka ,  Masakazu Hirose

发明人： Hideto Hidaka ,  Masakazu Hirose

IPC分类号： H03K300

CPC分类号： H03K19/00361

摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

摘要翻译： 当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。 当驱动晶体管导通时，输出节点以高速放电到地电位。 当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。 结果，输出节点的电位从高电平降低到中间电平，使得后续输出信号的幅度减小。 提供了可以有效地防止产生振铃而不增加访问时间的输出电路。 提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。 高速提供稳定的输出信号。

公开(公告)号：US06757191B2

公开(公告)日：2004-06-29

申请号：US10222793

申请日：2002-08-19

申请人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

发明人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

IPC分类号： G11C1114

CPC分类号： G11C11/16

摘要： A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

摘要翻译： 每个MTJ（磁性隧道结）存储单元的隧道磁阻元件连接在位线和带之间。 每个带由多个相同子阵列中的行方向上彼此相邻的隧道磁阻元件共享。 每个存取晶体管连接在对应的带和接地电压之间，并响应于相应的字线而导通/截止。 由于可以对每个隧道磁阻元件不具有存取晶体管的结构进行数据读取操作，因此可以减小阵列面积。

公开(公告)号：US06621306B2

公开(公告)日：2003-09-16

申请号：US10036406

申请日：2002-01-07

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： H03K19094

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356121

摘要： A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.

公开(公告)号：US06577522B2

公开(公告)日：2003-06-10

申请号：US10094918

申请日：2002-03-12

申请人： Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

发明人： Hideto Hidaka ,  Katsuhiro Suma ,  Takahiro Tsuruda

IPC分类号： G11C502

CPC分类号： H01L27/10897 ,  G11C11/404 ,  G11C11/4097 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203

摘要： A semiconductor memory device includes a plurality of N and P channel MOS transistors. The plurality of MOS transistors are formed on an SOI (Silicon On Insulator) substrate. Each MOS transistor includes a source region, a drain region, and a body region located between the source region and the drain region. The body region of at least one N channel MOS transistor is electrically fixed. The body region of at least one P channel MOS transistor is rendered floating.

公开(公告)号：US06538953B2

公开(公告)日：2003-03-25

申请号：US10103999

申请日：2002-03-25

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C800

CPC分类号： G11C11/406

摘要： A refresh address is set to a definite state prior to the rise of a clock signal, a refresh instruction is taken-in in synchronization with a clock signal and a refresh operation is performed according to the refresh instruction. Further, in a refresh operation, refresh is performed with a sub-word line being a unit; thereby enabling high speed refresh of memory sell data with a reduced current consumption.

公开(公告)号：US06469327B1

公开(公告)日：2002-10-22

申请号：US08900515

申请日：1997-07-25

申请人： Kenichi Yasuda ,  Hideto Hidaka ,  Mikio Asakura ,  Tsukasa Ooishi ,  Kei Hamade

发明人： Kenichi Yasuda ,  Hideto Hidaka ,  Mikio Asakura ,  Tsukasa Ooishi ,  Kei Hamade

IPC分类号： H01L2710

CPC分类号： H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L27/0207 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.

摘要翻译： 垫片排列在半导体芯片的中心区域中，并且还布置在芯片的中心部分的外周部分。 外周部分的焊盘与安装芯片的芯片焊盘电连接，绝缘材料插入其间。 通过芯片焊盘的寄生电容可以使供给位于外周部的焊盘的电位稳定，并且能够通过在树脂密封后除去一部分模制树脂来容易地外部监视焊盘的电位。 此外，由于焊盘的水平排列，可以将电压降压转换器布置成与焊盘和芯片的外周边一致，而不会造成区域损失。 在测试操作中，切换电路将焊盘的功能切换到另一焊盘，使得十字形布置的焊盘等价地布置成一行。

公开(公告)号：US06349054B1

公开(公告)日：2002-02-19

申请号：US09852087

申请日：2001-05-10

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C1115

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2207/002

摘要： In the data read operation, a memory cell and a dummy memory cell are respectively coupled to two bit lines of a selected bit line pair, and a data read current is supplied thereto. In the selected memory cell column, a read gate drives the respective voltages on a read data bus pair, according to the respective voltages on the bit lines. A data read circuit amplifies the voltage difference between the read data buses so as to output read data. The use of the read gate enables the read data buses to be disconnected from a data read current path. As a result, respective voltage changes on the bit lines are rapidly produced, whereby the data read speed can be increased.

公开(公告)号：US06337583B1

公开(公告)日：2002-01-08

申请号：US09571270

申请日：2000-05-15

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： H03K19094

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356121

摘要： A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.