公开(公告)号：US08324040B2

公开(公告)日：2012-12-04

申请号：US12785016

申请日：2010-05-21

申请人： Hiroyuki Ohta

发明人： Hiroyuki Ohta

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L29/7843 ,  H01L21/823412 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including an n-channel MISFET including source/drain regions 38 formed in a semiconductor substrate 10 with a channel region between them, and a gate electrode 44 of a metal silicide formed over the channel region with a gate insulating film 12 interposed therebetween; and an insulating film 46 formed over the gate electrode 44 from side walls of the gate electrode 44 to an upper surface of the gate electrode 44, having a tensile stress from 1.0 to 2.0 GPa and applying the tensile stress to the channel region.

摘要翻译： 一种半导体器件，包括n沟道MISFET，其包括形成在半导体衬底10中的沟道区域之间的源极/漏极区域38和在沟道区域上形成的金属硅化物的栅电极44，栅极绝缘膜12插入其间 ; 以及从栅电极44的侧壁到栅电极44的上表面的栅电极44的上方形成的绝缘膜46，拉伸应力为1.0〜2.0GPa，并对该沟道区施加拉伸应力。

公开(公告)号：US07906848B2

公开(公告)日：2011-03-15

申请号：US12389071

申请日：2009-02-19

申请人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

发明人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/53238 ,  H01L23/3128 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/0401

摘要： In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

摘要翻译： 在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。 在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触 形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

公开(公告)号：US07906798B2

公开(公告)日：2011-03-15

申请号：US11950102

申请日：2007-12-04

申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

IPC分类号： H01L27/092

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

公开(公告)号：US20110049533A1

公开(公告)日：2011-03-03

申请号：US12916953

申请日：2010-11-01

申请人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

发明人： Yosuke Shimamune ,  Hiroyuki Ohta ,  Akiyoshi Hatada ,  Akira Katakami ,  Naoyoshi Tamura

IPC分类号： H01L29/24

CPC分类号： H01L29/165 ,  H01L29/045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.

摘要翻译： 公开了一种制造半导体器件的方法，其能够抑制短沟道效应并改善载流子迁移率。 在该方法中，在对应于源极区和漏极区的硅衬底中形成沟槽。 当外延生长p型半导体混晶层以填充沟槽时，沟槽的表面被刻面划分，半导体混晶层的延伸部分形成在第二侧壁绝缘膜的底表面和 硅衬底和延伸部分与源极延伸区域和漏极延伸区域接触。

公开(公告)号：US07770462B2

公开(公告)日：2010-08-10

申请号：US12184104

申请日：2008-07-31

申请人： Hiroyuki Ohta ,  Takashi Sumigawa

发明人： Hiroyuki Ohta ,  Takashi Sumigawa

IPC分类号： G01B7/06

CPC分类号： G01L1/18

摘要： A mechanical quantity measuring apparatus is provided which can make highly precise measurements and is not easily affected by noise even when it is supplied an electricity through electromagnetic induction or microwaves. At least a strain sensor and an amplifier, an analog/digital converter, a rectification/detection/modulation-demodulation circuit, and a communication control circuit are formed in one and the same silicon substrate. Or, the silicon substrate is also formed at its surface with a dummy resistor which has its longitudinal direction set in a particular crystal orientation and which, together with the strain sensor, forms a Wheatstone bridge. With this arrangement, even when a current flowing through the sensor is reduced, measured data is prevented from being buried in noise, allowing the sensor to operate on a small power and to measure a mechanical quantity with high precision even when it is supplied electricity through electromagnetic induction or microwaves.

摘要翻译： 提供了能够进行高精度测量并且即使当通过电磁感应或微波供应电而不易受噪声影响的机械量测量装置。 至少一个应变传感器和放大器，模拟/数字转换器，整流/检测/调制解调电路和通信控制电路形成在同一个硅衬底中。 或者，硅衬底也在其表面上形成一个虚拟电阻器，该虚拟电阻器的纵向方向设置在特定的晶体取向中，并与应变传感器一起形成惠斯通电桥。 通过这种布置，即使当流过传感器的电流减小时，也可以防止测量数据被埋入噪声中，使得传感器能够以小功率工作，并且即使在通过电力供应通过时也以高精度测量机械量 电磁感应或微波。

公开(公告)号：US07759215B2

公开(公告)日：2010-07-20

申请号：US11723246

申请日：2007-03-19

申请人： Hiroyuki Ohta

发明人： Hiroyuki Ohta

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

摘要： The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film covering an inner surface of the isolation trench; forming a first silicon oxide film burying the isolation trench; etching and removing the first silicon oxide film in an upper region of the isolation trench; etching and removing the exposed second silicon nitride film; chemical-mechanical-polishing the second silicon oxide film; and etching and removing the exposed first silicon nitride film.

摘要翻译： 制造半导体器件的方法具有以下步骤：通过使用包括第一氮化硅膜并具有窗口的图案作为掩模来蚀刻半导体衬底以形成隔离沟槽; 沉积覆盖隔离沟槽的内表面的第二氮化硅膜; 形成掩埋隔离沟槽的第一氧化硅膜; 蚀刻并去除隔离沟槽的上部区域中的第一氧化硅膜; 蚀刻和去除暴露的第二氮化硅膜; 化学机械抛光第二氧化硅膜; 并蚀刻和去除暴露的第一氮化硅膜。

公开(公告)号：US20100154555A1

公开(公告)日：2010-06-24

申请号：US12719977

申请日：2010-03-09

申请人： Takashi Sumigawa ,  Hiroyuki Ohta

发明人： Takashi Sumigawa ,  Hiroyuki Ohta

IPC分类号： G01B7/16

CPC分类号： G01B7/18 ,  G01B7/16 ,  G01B7/20 ,  G01L1/2206 ,  G01L1/2262 ,  G01L5/0047

摘要： An apparatus structure and measurement method are provided to retain high precision and high reliability of a semiconductor mechanical quantity measuring apparatus which senses a mechanical quantity and transmits measured information wirelessly. As to a silicon substrate of the semiconductor mechanical quantity measuring apparatus, for example, a ratio of a substrate thickness to a substrate length along a measurement direction is set small, and a ratio of a substrate thickness to a substrate length along a direction perpendicular to the measurement direction is set small. The apparatus upper surface is covered with a protective member. It is possible to measure a strain along a particular direction and realize mechanical quantity measurement with less error and high precision. An impact resistance and environment resistance of the apparatus itself can be improved.

摘要翻译： 提供了一种装置结构和测量方法，以保持半导体机械量测量装置的高精度和高可靠性，该装置检测机械量并无线传送测量信息。 对于半导体机械量测量装置的硅衬底，例如，沿着测量方向将衬底厚度与衬底长度的比率设置得较小，并且沿着垂直于半导体机械量测量装置的方向的衬底厚度与衬底长度的比率 测量方向设定得很小。 设备上表面被保护构件覆盖。 可以测量特定方向的应变，实现误差小，精度更高的机械量测量。 可以提高装置本身的耐冲击性和耐环境性。

公开(公告)号：US07707894B2

公开(公告)日：2010-05-04

申请号：US12210261

申请日：2008-09-15

申请人： Takashi Sumigawa ,  Hiroyuki Ohta

发明人： Takashi Sumigawa ,  Hiroyuki Ohta

IPC分类号： G01B7/16

CPC分类号： G01B7/18 ,  G01B7/16 ,  G01B7/20 ,  G01L1/2206 ,  G01L1/2262 ,  G01L5/0047

摘要： An apparatus structure and measurement method are provided to retain high precision and high reliability of a semiconductor mechanical quantity measuring apparatus which senses a mechanical quantity and transmits measured information wirelessly. As to a silicon substrate of the semiconductor mechanical quantity measuring apparatus, for example, a ratio of a substrate thickness to a substrate length along a measurement direction is set small, and a ratio of a substrate thickness to a substrate length along a direction perpendicular to the measurement direction is set small. The apparatus upper surface is covered with a protective member. It is possible to measure a strain along a particular direction and realize mechanical quantity measurement with less error and high precision. An impact resistance and environment resistance of the apparatus itself can be improved.

摘要翻译： 提供了一种装置结构和测量方法，以保持半导体机械量测量装置的高精度和高可靠性，该装置检测机械量并无线传送测量信息。 对于半导体机械量测量装置的硅衬底，例如，沿着测量方向将衬底厚度与衬底长度的比率设置得较小，并且沿着垂直于半导体机械量测量装置的方向的衬底厚度与衬底长度的比率 测量方向设定得很小。 设备上表面被保护构件覆盖。 可以测量特定方向的应变，实现误差小，精度更高的机械量测量。 可以提高装置本身的耐冲击性和耐环境性。

公开(公告)号：US07678641B2

公开(公告)日：2010-03-16

申请号：US11211103

申请日：2005-08-25

申请人： Toshifumi Mori ,  Katsuaki Ookoshi ,  Takashi Watanabe ,  Hiroyuki Ohta

发明人： Toshifumi Mori ,  Katsuaki Ookoshi ,  Takashi Watanabe ,  Hiroyuki Ohta

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  H01L21/76229 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： There is provided a semiconductor device having a device isolation region of STI structure formed on a silicon substrate so as to define a device region, wherein the device isolation region comprises a device isolation trench formed in the silicon substrate, and a device isolation insulation film filling the device isolation trench. At least a surface part of the device isolation insulation film is formed of an HF-resistant film.

摘要翻译： 提供了一种在硅衬底上形成有STI结构的器件隔离区域以限定器件区域的半导体器件，其中器件隔离区域包括形成在硅衬底中的器件隔离沟槽，以及器件隔离绝缘膜填充 器件隔离沟槽。 器件隔离绝缘膜的至少表面部分由耐高温膜形成。

公开(公告)号：US07518202B2

公开(公告)日：2009-04-14

申请号：US11349913

申请日：2006-02-09

申请人： Hisashi Tanie ,  Takashi Sumigawa ,  Hiroyuki Ohta

发明人： Hisashi Tanie ,  Takashi Sumigawa ,  Hiroyuki Ohta

IPC分类号： H01L29/84

CPC分类号： G01B7/18 ,  G01L1/2293

摘要： A semiconductor mechanical quantity measuring apparatus in which the reverse surface of a strain-detecting semiconductor element is bonded to an object of measurement, and a member having a small elastic modulus is interposed between the wiring board for supporting the strain-detecting semiconductor element and the strain-detecting semiconductor element. It then becomes possible to reduce an undesirable effect that the rigidity and thermal deformation of the wiring board have on the strain-detecting semiconductor element, while supporting the strain-detecting semiconductor element.

摘要翻译： 一种半导体机械量测量装置，其中应变检测用半导体元件的反面与测量对象接合，并且具有小弹性模量的构件插入在用于支撑应变检测用半导体元件的布线基板和 应变检测半导体元件。 然后，可以减少在应变检测用半导体元件上配线基板的刚性和热变形对应变检测用半导体元件的不良影响。