公开(公告)号：US06459641B2

公开(公告)日：2002-10-01

申请号：US09834945

申请日：2001-04-16

申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

摘要翻译： 本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

公开(公告)号：US06396758B2

公开(公告)日：2002-05-28

申请号：US09793603

申请日：2001-02-27

申请人： Hitoshi Ikeda ,  Tatsuya Kanda ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

发明人： Hitoshi Ikeda ,  Tatsuya Kanda ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.

摘要翻译： 具有自刷新操作的半导体存储器件包括检测电路，当检测到给定输入信号的变化时产生检测信号;以及比较器电路，将检测信号与内部产生的刷新请求信号进行比较，并生成表示 电路操作。

公开(公告)号：US06353561B1

公开(公告)日：2002-03-05

申请号：US09397845

申请日：1999-09-17

申请人： Akihiro Funyu ,  Shinya Fujioka ,  Yasuharu Sato ,  Toshiya Uchida

发明人： Akihiro Funyu ,  Shinya Fujioka ,  Yasuharu Sato ,  Toshiya Uchida

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093

摘要： A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.

摘要翻译： 诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。 该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。 这允许在外部时钟的每个周期获取多于一个外部命令。 获取的外部命令被提供给命令解码器进行解码。 当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

公开(公告)号：US06246620B1

公开(公告)日：2001-06-12

申请号：US09533759

申请日：2000-03-23

申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

公开(公告)号：US06191999B1

公开(公告)日：2001-02-20

申请号：US08993139

申请日：1997-12-18

申请人： Waichirou Fujieda ,  Shinya Fujioka ,  Tadao Aikawa

发明人： Waichirou Fujieda ,  Shinya Fujioka ,  Tadao Aikawa

IPC分类号： G11C800

CPC分类号： G11C8/14 ,  G11C8/10

摘要： A semiconductor memory device using hierarchical word decoding for word selection includes memory-cell areas, each of which is provided for a corresponding one of column blocks. The semiconductor memory device further includes sub-word lines provided for each one of the column blocks and extending over a corresponding one of the memory-cell areas, and sub-word decoders provided on either side of a given one of the memory-cell areas to select one of the sub-word lines only with respect to the given one of the memory-cell areas.

摘要翻译： 使用用于字选择的分层字解码的半导体存储器件包括存储单元区域，每个区域被提供给相应的列块。 半导体存储器件还包括为每个列块提供的子字线，并且在相应的一个存储单元区域上延伸，并且在给定的一个存储单元区域的两侧提供的子字解码器 仅相对于给定的一个存储单元区域来选择一个子字线。

公开(公告)号：US6108243A

公开(公告)日：2000-08-22

申请号：US383014

申请日：1999-08-25

申请人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

发明人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/2281 ,  G11C2207/229

摘要： The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.

摘要翻译： 本发明是一种FCRAM，包括用于执行命令解码的第一级，用于执行读出放大器激活的第二级，以及在流水线结构中执行数据输入和输出的第三级，并行传输的多个数据位 在读出放大器和第三级之间，其中读出放大器被自动去激活，并且在数据已经在感测放大器和第三级之间并行传送之后，响应于标准的读或写命令来执行复位操作。

公开(公告)号：US6088291A

公开(公告)日：2000-07-11

申请号：US147600

申请日：1999-01-29

申请人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

发明人： Shinya Fujioka ,  Masao Taguchi ,  Waichirou Fujieda ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Takayuki Nagasawa

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4094 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C2207/005 ,  G11C2207/065

摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.

摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。 第WO98 / 56004号公报 日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。

公开(公告)号：US5668763A

公开(公告)日：1997-09-16

申请号：US606819

申请日：1996-02-26

申请人： Shinya Fujioka ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki

发明人： Shinya Fujioka ,  Atsushi Hatakeyama ,  Hirohiko Mochizuki

IPC分类号： G11C29/00

CPC分类号： G11C29/808

摘要： A semiconductor memory has a plurality of memory arrays, and a plurality of selection circuits. Each of the memory arrays has a plurality of memory blocks. The selection circuits is provided to the memory arrays and is used to independently disable a defective memory block and select a normal memory block in the memory array. Therefore, the semiconductor memory enables to increase the number of partial good memories (half good memories: half capacity memory), and to increase a product yield.

摘要翻译： 半导体存储器具有多个存储器阵列和多个选择电路。 每个存储器阵列具有多个存储器块。 选择电路被提供给存储器阵列，并且用于独立地禁用缺陷存储器块并选择存储器阵列中的正常存储器块。 因此，半导体存储器能够增加部分良好存储器的数量（半好的存储器：半容量存储器），并且增加产品产量。

公开(公告)号：US20130182559A1

公开(公告)日：2013-07-18

申请号：US13553631

申请日：2012-07-19

申请人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani ,  Hideki Endo

发明人： Shinya Fujioka ,  Yoshihiro Ashi ,  Masahiko Mizutani ,  Hideki Endo

IPC分类号： H04L12/24

CPC分类号： H04L41/0668 ,  H04L43/0817

摘要： A transmission network is comprised of a network management system for collectively managing and controlling a plurality of transmission devices coupled mutually through transmission routes and the transmission network as well. The network management system includes a plane management table adapted to manage transmission planes defined as a set of paths in the transmission network, and the plane management table has the function to set and manage a transmission plane (working plane) applied during normal operation and besides, a single or a plurality of transmission planes (protection planes) applicable in the event of occurrence of a fault in the transmission network. Then, when a fault occurs in the transmission network, the network management system changes the applied plane to a suitable transmission plane.

公开(公告)号：US07746718B2

公开(公告)日：2010-06-29

申请号：US11998428

申请日：2007-11-30

申请人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

发明人： Yasuyuki Eguchi ,  Shinya Fujioka ,  Yoshiaki Okuyama

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/12 ,  G11C11/40622

摘要： A refresh register stores disable block information indicating a memory block whose refresh operation is to be disabled. A refresh control circuit periodically executes the refresh operation of a memory block except the memory block corresponding to the disable block information. During an access cycle to one of the memory blocks, the register control circuit writes the disable block information to the refresh register according to an external input. Consequently, in order to rewrite the refresh register, it is not necessary to use an additional operation cycle to the access cycle. Since there is no need to insert an extra operation cycle, it is possible to change a memory area to be refreshed without lowering effective efficiency of access cycles. As a result, power consumption can be reduced.

摘要翻译： 刷新寄存器存储指示将被禁用刷新操作的存储器块的禁止块信息。 刷新控制电路周期性地执行除了与禁用块信息相对应的存储块之外的存储器块的刷新操作。 在对存储器块之一的访问周期期间，寄存器控制电路根据外部输入将该禁止块信息写入刷新寄存器。 因此，为了重写刷新寄存器，不需要对访问周期使用附加的操作周期。 由于不需要插入额外的操作周期，因此可以改变要刷新的存储器区域，而不会降低访问周期的有效效率。 结果，可以降低功耗。