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    Semiconductor integrated circuit and method for controlling the same
    1.
    发明授权
    Semiconductor integrated circuit and method for controlling the same 有权
    半导体集成电路及其控制方法

    公开(公告)号：US06353561B1

    公开(公告)日：2002-03-05

    申请号：US09397845

    申请日：1999-09-17

    申请人： Akihiro Funyu ,  Shinya Fujioka ,  Yasuharu Sato ,  Toshiya Uchida

    发明人： Akihiro Funyu ,  Shinya Fujioka ,  Yasuharu Sato ,  Toshiya Uchida

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093

    摘要： A semiconductor memory device, such as a synchronous DRAM, receives external commands and an external clock signal via input buffers. The device generates internal clock signals having a slower frequency than the external clock signal and uses the internal clock signals to acquire the external command. This allows more than one external command to be acquired for each cycle of the external clock. The acquired external commands are provided to command decoders for decoding. A mask circuit is connected to the decoder circuits and inhibits the decoding circuits, except for a first one of the decoding circuits, from decoding the external commands for a predetermined time period, when the first decoder circuit is decoding the external commands.

    摘要翻译： 诸如同步DRAM的半导体存储器件经由输入缓冲器接收外部命令和外部时钟信号。 该器件产生的频率低于外部时钟信号的内部时钟信号，并使用内部时钟信号来获取外部命令。 这允许在外部时钟的每个周期获取多于一个外部命令。 获取的外部命令被提供给命令解码器进行解码。 当第一解码器电路解码外部命令时，掩码电路连接到解码器电路，并且禁止解码电路以外的第一解码电路在预定时间段内解码外部命令。

    Semiconductor integrated circuit memory
    2.
    发明授权
    Semiconductor integrated circuit memory 有权
    半导体集成电路存储器

    公开(公告)号：US06185149B2

    公开(公告)日：2001-02-06

    申请号：US09340147

    申请日：1999-06-28

    申请人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    发明人： Shinya Fujioka ,  Masao Taguchi ,  Yasuharu Sato ,  Takaaki Suzuki ,  Tadao Aikawa ,  Yasurou Matsuzaki ,  Toshiya Uchida

    IPC分类号： G11C800

    CPC分类号： G11C7/1018 ,  G11C7/1072

    摘要： A semiconductor memory includes memory cell blocks, a burst-length information generating circuit which generates burst-length information based on a burst length, and a block enable circuit which receives the burst-length information. The block enable circuit selectively enables one of the memory cell blocks when the burst length is equal to or shorter than a predetermined burst length and selectively enables a plurality of memory cell blocks based on the burst length when the burst length is longer than the predetermined burst length. Data are read from the above-mentioned one or plurality of memory cell blocks.

    摘要翻译： 半导体存储器包括存储单元块，基于突发长度生成突发长度信息的突发长度信息产生电路，以及接收脉冲串长度信息的块使能电路。 当突发长度等于或小于预定突发长度时，块使能电路选择性地启用存储单元块中的一个，并且当突发长度长于预定突发时，基于脉冲串长度选择性地启用多个存储单元块 长度。 从上述一个或多个存储单元块读取数据。

    Semiconductor memory device
    4.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06529439B2

    公开(公告)日：2003-03-04

    申请号：US09789514

    申请日：2001-02-22

    申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C5/06

    摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06614712B2

    公开(公告)日：2003-09-02

    申请号：US10329669

    申请日：2002-12-27

    申请人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    发明人： Toshiya Uchida ,  Kota Hara ,  Shinya Fujioka

    IPC分类号： G11C800

    CPC分类号： G11C8/08 ,  G11C5/06

    摘要： A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

    Memory device, memory controller and memory system
    9.
    发明授权
    Memory device, memory controller and memory system 有权
    内存设备，内存控制器和内存系统

    公开(公告)号：US08015389B2

    公开(公告)日：2011-09-06

    申请号：US12000953

    申请日：2007-12-19

    申请人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    发明人： Takahiko Sato ,  Toshiya Uchida ,  Tatsuya Kanda ,  Tetsuo Miyamoto ,  Satoru Shirakawa ,  Yoshinobu Yamamoto ,  Tatsushi Otsuka ,  Hidenaga Takahashi ,  Masanori Kurita ,  Shinnosuke Kamata ,  Ayako Sato

    IPC分类号： G06F12/06

    CPC分类号： G11C11/4087 ,  G09G5/393 ,  G09G5/395 ,  G11C8/12

    摘要： An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals. Each of the memory unit areas stores therein data of a plurality of bytes or bits corresponding to the plurality of input/output terminals respectively, and the memory cell array and the input/output unit access a plurality of bytes or bits stored in a first memory unit area corresponding to the input address and in a second memory unit area adjacent to the first memory unit on the basis of the input address and combination information of the bytes or bits in response to a first operation code, and then, from the plurality of bytes or bits within the accessed first and second memory unit areas, associate a combination of the plurality of bytes or bits based on the combination information, with the plurality of input/output terminals.

    摘要翻译： 提供能够有效地访问二维排列数据的矩形区域的图像存储器，图像存储器系统和存储器控制器。 存储装置具有：具有多个存储单元区域的存储单元阵列，每个存储单元区域由地址选择; 多个输入/输出端子; 以及设置在存储单元阵列和多个输入/输出端子之间的输入/输出单元。 每个存储单元区域分别存储与多个输入/输出端子相对应的多个字节或位的数据，并且存储单元阵列和输入/输出单元访问存储在第一存储器中的多个字节或位 基于与第一操作码相对应的字节或比特的输入地址和组合信息，与第一存储器单元相邻的第二存储器单元区域中的对应于输入地址的单位区域和与第一存储器单元相邻的第二存储单元区域中， 在所访问的第一和第二存储器单元区域内的字节或比特，基于组合信息将多个字节或比特的组合与多个输入/输出终端相关联。