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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06396758B2

    公开(公告)日：2002-05-28

    申请号：US09793603

    申请日：2001-02-27

    申请人： Hitoshi Ikeda ,  Tatsuya Kanda ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

    发明人： Hitoshi Ikeda ,  Tatsuya Kanda ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

    IPC分类号： G11C700

    CPC分类号： G11C11/406

    摘要： A semiconductor memory device having a self-refresh operation includes a detection circuit generating a detection signal when detecting a change of a given input signal, and a comparator circuit comparing the detection signal with a refresh request signal internally generated and generating a control signal indicative of a circuit operation.

    摘要翻译： 具有自刷新操作的半导体存储器件包括检测电路，当检测到给定输入信号的变化时产生检测信号;以及比较器电路，将检测信号与内部产生的刷新请求信号进行比较，并生成表示 电路操作。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08111575B2

    公开(公告)日：2012-02-07

    申请号：US12684652

    申请日：2010-01-08

    申请人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    发明人： Kaoru Mori ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    IPC分类号： G11C5/14

    CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

    摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

    摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100110818A1

    公开(公告)日：2010-05-06

    申请号：US12684652

    申请日：2010-01-08

    申请人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    发明人： Kaoru MORI ,  Shinya Fujioka ,  Yoshitaka Takahashi ,  Jun Ohno ,  Akihiro Funyu ,  Shinichiro Suzuki

    IPC分类号： G11C7/00 ,  H03K17/00 ,  H03K17/56 ,  G11C8/00

    CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C11/40626 ,  G11C11/4072 ,  G11C11/4074

    摘要： There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

    摘要翻译： 提供了一种半导体器件，包括：温度传感器检测温度; 当从电源线供给电源电压时工作的内部电路; 连接在电源线和内部电路之间的开关; 以及控制电路，其进行控制，其中，在由所述温度传感器检测到的温度高于阈值的情况下，当所述内部电路工作时所述开关接通，并且当所述内部电路为 在不工作的情况下，并且在由温度传感器检测到的温度低于阈值的情况下，当内部电路运行并且不工作时，开关导通。

    Semiconductor memory device having a self-refresh operation
    4.
    发明授权
    Semiconductor memory device having a self-refresh operation 失效
    具有自刷新操作的半导体存储器件

    公开(公告)号：US06404688B2

    公开(公告)日：2002-06-11

    申请号：US09791839

    申请日：2001-02-26

    申请人： Yoshiaki Okuyama ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

    发明人： Yoshiaki Okuyama ,  Yoshitaka Takahashi ,  Shinya Fujioka ,  Akihiro Funyu

    IPC分类号： G11C700

    CPC分类号： G11C11/406 ,  G11C7/1045

    摘要： A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit receiving a second signal that specifies a second self-refresh cycle via a terminal that is used in common to another signal, and a third circuit generating a pulse signal having one of the first and second self-refresh cycles, the pulse signal being related to the self-refresh operation.

    摘要翻译： 具有自刷新操作的半导体存储器件包括：第一电路，产生由设置在半导体存储器件中的非易失性电路元件指定第一自刷新周期的第一信号;第二电路，接收指定第 第二自刷新周期经由与另一信号共同使用的端子，以及第三电路，产生具有第一和第二自刷新周期中的一个的脉冲信号，所述脉冲信号与自刷新操作相关。

    Semiconductor memory device having an SRAM and a DRAM on a single chip
    5.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06735141B2

    公开(公告)日：2004-05-11

    申请号：US09917913

    申请日：2001-07-31

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C700

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Semiconductor memory device having an SRAM and a DRAM on a single chip
    7.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06292426B1

    公开(公告)日：2001-09-18

    申请号：US09531498

    申请日：2000-03-21

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C800

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless
    9.
    发明授权
    Semiconductor storage device conducting a late-write operation and controlling a test read-operation to read data not from a data latch circuit but from a memory core circuit regardless 有权
    半导体存储装置进行后期写入操作并且控制测试读取操作以不是从数据锁存电路而是从存储器核心电路读取数据，而不管前面的地址和当前地址是否彼此匹配

    公开(公告)号：US06700816B2

    公开(公告)日：2004-03-02

    申请号：US10287495

    申请日：2002-11-05

    申请人： Yoshitaka Takahashi ,  Hitoshi Ikeda ,  Shinya Fujioka

    发明人： Yoshitaka Takahashi ,  Hitoshi Ikeda ,  Shinya Fujioka

    IPC分类号： G11C700

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/00 ,  G11C8/06

    摘要： A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.

    摘要翻译： 半导体存储装置进行后期写入操作。 半导体存储装置包括：存储数据的存储器核心电路; 数据锁存电路，存储对应于先前的写入操作的先前数据; 比较与前一写入操作相对应的前一地址和对应于当前读操作的当前地址的地址比较电路，以便确定前一地址和当前地址是否彼此匹配; 和控制电路。 无论前一地址和当前地址是否彼此匹配，控制电路控制测试读取操作以从存储器核心电路读取数据。

    Semiconductor memory device for masking all bits in a test write operation
    10.
    发明授权
    Semiconductor memory device for masking all bits in a test write operation 有权
    用于在测试写入操作中屏蔽所有位的半导体存储器件

    公开(公告)号：US06778451B2

    公开(公告)日：2004-08-17

    申请号：US10171686

    申请日：2002-06-17

    申请人： Yoshitaka Takahashi ,  Hitoshi Ikeda ,  Shinya Fujioka

    发明人： Yoshitaka Takahashi ,  Hitoshi Ikeda ,  Shinya Fujioka

    IPC分类号： G11C2900

    CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/00 ,  G11C8/06

    摘要： A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.

    摘要翻译： 半导体存储装置进行后期写入操作。 半导体存储装置包括：存储数据的存储器核心电路; 数据锁存电路，存储对应于先前的写入操作的先前数据; 比较与前一写入操作相对应的前一地址和对应于当前读操作的当前地址的地址比较电路，以便确定前一地址和当前地址是否彼此匹配; 和控制电路。 控制电路控制测试读取操作以从存储器核心电路读取数据，而不管前面的地址和当前地址是否彼此匹配。