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57 条记录 (耗时 0.043 秒)

    Defocus determination method using sub-resolution feature (SRF) printing
    53.
    发明授权
    Defocus determination method using sub-resolution feature (SRF) printing 有权
    散焦确定方法使用分辨率特征（SRF）打印

    公开(公告)号：US07840932B2

    公开(公告)日：2010-11-23

    申请号：US11746970

    申请日：2007-05-10

    申请人： Yong Seok Choi

    发明人： Yong Seok Choi

    IPC分类号： G06F17/50

    CPC分类号： G03B27/42 ,  G03F7/70641

    摘要： The present application is directed to apparatus and methods for determining a magnitude of defocus and a direction of defocus for a photolithography process. A sub-resolution feature on a reticle which is not printed on a wafer at the best focus offset, but is formed on a wafer at some defocus during the photolithography process is analyzed to determine the magnitude and direction of defocus. The magnitude and direction of defocus are used to adjust the photolithography process to an optimal focus based on the determined magnitude of defocus and the determined direction of defocus.

    摘要翻译： 本申请涉及用于确定用于光刻工艺的散焦大小和散焦方向的装置和方法。 分析光掩膜上的亚分辨率特征，其不以最佳聚焦偏移印刷在晶片上，而是在光刻工艺期间在一些散焦处形成在晶片上，以确定散焦的大小和方向。 散焦的大小和方向用于基于确定的散焦的大小和确定的散焦方向将光刻处理调整到最佳焦点。

    Piercing device of hydroforming mold
    54.
    发明授权
    Piercing device of hydroforming mold 有权

    公开(公告)号：US07552609B2

    公开(公告)日：2009-06-30

    申请号：US12006369

    申请日：2008-01-02

    申请人： Yong Seok Choi

    发明人： Yong Seok Choi

    IPC分类号： B21D53/88 ,  B21D26/02

    CPC分类号： B21D26/035 ,  B21D28/24 ,  B21D28/34 ,  Y10T29/49805 ,  Y10T83/0591

    摘要： Disclosed is a piercing device of a hydroforming mold with a lower steel having a cavity therein, which can make the replacement of the pierce punch easier. The piercing device comprises: a pierce punch, the front edge portion of which is inserted into the cavity, for punching a hole through a molding material; a pierce cylinder for providing hydraulic pressure; a rod connected to the pierce cylinder, which is to be operated by the hydraulic pressure; and a pierce block connecting the rod and the pierce punch, wherein the length between the front edge portion of the rod and the pierce punch is greater than the length of the pierce punch.

    TRI-LAYER PLASMA ETCH RESIST REWORK
    55.
    发明申请
    TRI-LAYER PLASMA ETCH RESIST REWORK 有权
    三层等离子体蚀刻反应

    公开(公告)号：US20090050604A1

    公开(公告)日：2009-02-26

    申请号：US11843361

    申请日：2007-08-22

    申请人： Jeannette Michelle Jacques ,  Yong Seok Choi

    发明人： Jeannette Michelle Jacques ,  Yong Seok Choi

    IPC分类号： G03F1/00

    CPC分类号： H01L21/31144 ,  H01L21/02079 ,  H01L21/0271

    摘要： Exemplary embodiments provide a tri-layer resist (TLR) stack used in a photolithographic process, and methods for resist reworking by a single plasma etch process. The single plasma etch process can be used to remove one or more portions/layers of the TLR stack that needs to be reworked in a single process. The removed portions/layers can then be re-formed and resulting in a reworked TLR stack for subsequent photo-resist (PR) processing. The disclosed plasma-etch resist rework method can be a fast, simple, and cost effective process used in either single or dual damascene tri-layer patterning processes for the fabrication of, for example, sub 45-nm node semiconductor structures.

    摘要翻译： 示例性实施例提供了在光刻工艺中使用的三层抗蚀剂（TLR）堆叠，以及通过单个等离子体蚀刻工艺来抵抗再加工的方法。 单个等离子体蚀刻工艺可用于去除在单个工艺中需要重新加工的TLR堆叠的一个或多个部分/层。 然后可以重新形成去除的部分/层，并导致用于随后的光致抗蚀剂（PR）处理的返工TLR堆叠。 所公开的等离子体蚀刻抗蚀剂返修方法可以是用于制造例如子45nm节点半导体结构的单镶嵌或双镶嵌三层图案化工艺中的快速，简单和成本有效的工艺。

    POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS
    56.
    发明申请
    POISON-FREE AND LOW ULK DAMAGE INTEGRATION SCHEME FOR DAMASCENE INTERCONNECTS 有权
    无连接和低ULK损伤集成方案用于大型互连

    公开(公告)号：US20080305625A1

    公开(公告)日：2008-12-11

    申请号：US11759451

    申请日：2007-06-07

    申请人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    发明人： Ping Jiang ,  William W. Dostalik ,  Yong Seok Choi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76811 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a dual-damascene structure is disclosed. A lower dielectric hardmask layer and an upper dielectric hardmask layer are deposited on an ultra low-k film. A first via is formed in the upper hardmask layer. Next, a first trench is formed using the tri-layer resist scheme. Finally, a full via and a full trench are formed simultaneously. An optional etch-stop layer can be used in the ultra low-k layer to control trench depth.

    摘要翻译： 公开了一种形成双镶嵌结构的方法。 在超低k膜上沉积下介电硬掩模层和上绝缘硬掩模层。 在上部硬掩模层中形成第一通孔。 接下来，使用三层抗蚀剂方案形成第一沟槽。 最后，同时形成完整通孔和全沟槽。 可以在超低k层中使用可选的蚀刻停止层来控制沟槽深度。