公开(公告)号：US09435967B2

公开(公告)日：2016-09-06

申请号：US14993049

申请日：2016-01-11

Applicant: INTEL CORPORATION

Inventor： Henning Braunisch ,  Shawna M. Liff ,  Peter L. Chang

IPC: G02B6/12 ,  G02B6/42

CPC classification number: G02B6/4261 ,  G02B6/12 ,  G02B6/4201 ,  G02B6/4239 ,  G02B6/4246 ,  G02B6/4256 ,  G02B6/4257 ,  G02B6/4269 ,  G02B6/4278 ,  G02B6/4292 ,  G02B6/46 ,  Y10T29/49128

Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例提供光学连接技术和配置。 在一个实施例中，一种装置包括用于安装在封装基板的表面上的插座，该插座具有可插接表面以接收光耦合器插头，使得光耦合器插头与光电组件的一个或多个光学孔径光学对准 其被配置为当所述光电组件固定到所述封装衬底时，使用所述一个或多个光学孔在基本上垂直于所述封装衬底的表面的方向上发射和/或接收光。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160124166A1

公开(公告)日：2016-05-05

申请号：US14993049

申请日：2016-01-11

Applicant: INTEL CORPORATION

Inventor： Henning Braunisch ,  Shawna M. Liff ,  Peter L. Chang

IPC: G02B6/42

CPC classification number: G02B6/4261 ,  G02B6/12 ,  G02B6/4201 ,  G02B6/4239 ,  G02B6/4246 ,  G02B6/4256 ,  G02B6/4257 ,  G02B6/4269 ,  G02B6/4278 ,  G02B6/4292 ,  G02B6/46 ,  Y10T29/49128

Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a receptacle for mounting on a surface of a package substrate, the receptacle having a pluggable surface to receive an optical coupler plug such that the optical coupler plug is optically aligned with one or more optical apertures of an optoelectronic assembly that is configured to emit and/or receive light using the one or more optical apertures in a direction that is substantially perpendicular to the surface of the package substrate when the optoelectronic assembly is affixed to the package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US12255158B2

公开(公告)日：2025-03-18

申请号：US16911543

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Diego Correas-Serrano ,  Henning Braunisch

IPC: H01L23/66 ,  H01L23/498 ,  H01P3/00 ,  H01P3/08

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US12242290B2

公开(公告)日：2025-03-04

申请号：US17484286

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  William J. Lambert ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini ,  Henning Braunisch ,  Stephen Morein ,  Aleksandar Aleksov ,  Feras Eid

IPC: G05F1/44 ,  H01L23/50 ,  H01L25/065

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US12126068B2

公开(公告)日：2024-10-22

申请号：US16912027

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Diego Correas-Serrano ,  Georgios Dogiamis ,  Henning Braunisch ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing

IPC: H01P3/16

CPC classification number: H01P3/16

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US12113026B2

公开(公告)日：2024-10-08

申请号：US18377991

申请日：2023-10-09

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L23/5385 ,  H01L23/13 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L21/6835 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/49175 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US11876053B2

公开(公告)日：2024-01-16

申请号：US17144130

申请日：2021-01-07

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L23/5385 ,  H01L23/13 ,  H01L23/5381 ,  H01L24/14 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L21/6835 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/141 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/49175 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/00 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US11764452B2

公开(公告)日：2023-09-19

申请号：US17672876

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Adel A. Elsherbini ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan

IPC: H01P3/16 ,  H01L23/66 ,  H01P11/00 ,  H04B10/2581

CPC classification number: H01P3/16 ,  H01L23/66 ,  H01P11/006 ,  H01L2223/6627 ,  H04B10/2581

Abstract: Disclosed herein are various designs for dielectric waveguides, as well as methods of manufacturing such waveguides. One type of dielectric waveguides described herein includes waveguides with one or more cavities in the dielectric waveguide material. Another type of dielectric waveguides described herein includes waveguides with a conductive ridge in the dielectric waveguide material. Dielectric waveguides described herein may be dispersion reduced dielectric waveguides, compared to conventional dielectric waveguides, and may be designed to adjust the difference in the group delay between the lower frequencies and the higher frequencies of a chosen bandwidth.

公开(公告)号：US20230098957A1

公开(公告)日：2023-03-30

申请号：US17485235

申请日：2021-09-24

Applicant: INTEL CORPORATION

Inventor： Feras Eid ,  Aleksandar Aleksov ,  Adel Elsherbini ,  Henning Braunisch

IPC: H01L23/00

Abstract: A conformal power delivery structure, a three-dimensional (3D) stacked die assembly, a system including the 3D stacked die assembly, and a method of forming the conformal power delivery structure. The power delivery structure includes a package substrate, a die adjacent to and electrically coupled to the package substrate; a first power plane adjacent the upper surface of the package substrate and electrically coupled thereto; a second power plane at least partially within recesses defined by the first power plane and having a lower surface that conforms with the upper surface of the first power plane; and a dielectric material between the first power plane and the second power plane.

公开(公告)号：US20230094979A1

公开(公告)日：2023-03-30

申请号：US17484299

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Feras Eid ,  Adel Elsherbini ,  Stephen Morein ,  Yoshihiro Tomita ,  Thomas L. Sounart ,  Johanna Swan ,  Brandon M. Rawlings

IPC: H01L23/50 ,  H01L23/532

Abstract: Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.