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    SRAM WITH P-TYPE ACCESS TRANSISTORS AND COMPLEMENTARY FIELD-EFFECT TRANSISTOR TECHNOLOGY
    51.
    发明公开
    SRAM WITH P-TYPE ACCESS TRANSISTORS AND COMPLEMENTARY FIELD-EFFECT TRANSISTOR TECHNOLOGY 审中-公开

    公开(公告)号：US20230284427A1

    公开(公告)日：2023-09-07

    申请号：US17686241

    申请日：2022-03-03

    Applicant: Intel Corporation

    Inventor： Charles AUGUSTINE ,  Seenivasan SUBRAMANIAM ,  Patrick MORROW ,  Muhammad M. KHELLAH

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419

    Abstract: Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.

    ISOLATION WALLS FOR VERTICALLY STACKED TRANSISTOR STRUCTURES
    53.
    发明申请
    ISOLATION WALLS FOR VERTICALLY STACKED TRANSISTOR STRUCTURES 有权

    公开(公告)号：US20220115372A1

    公开(公告)日：2022-04-14

    申请号：US17555296

    申请日：2021-12-17

    Applicant: Intel Corporation

    Inventor： Aaron LILAK ,  Patrick MORROW ,  Gilbert DEWEY ,  Willy RACHMADY ,  Rishabh MEHANDRU

    IPC: H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

    CAPACITANCE REDUCTION FOR SEMICONDUCTOR DEVICES BASED ON WAFER BONDING
    56.
    发明申请
    CAPACITANCE REDUCTION FOR SEMICONDUCTOR DEVICES BASED ON WAFER BONDING 审中-公开

    公开(公告)号：US20200303238A1

    公开(公告)日：2020-09-24

    申请号：US16358520

    申请日：2019-03-19

    Applicant: Intel Corporation

    Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Hui Jae YOO ,  Patrick MORROW ,  Kevin LIN

    IPC: H01L21/768 ,  H01L29/417 ,  H01L21/762 ,  H01L21/683 ,  H01L23/31

    Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

    3D FLOATING-GATE MULTIPLE-INPUT DEVICE
    57.
    发明申请
    3D FLOATING-GATE MULTIPLE-INPUT DEVICE 审中-公开

    公开(公告)号：US20200258894A1

    公开(公告)日：2020-08-13

    申请号：US16272816

    申请日：2019-02-11

    Applicant: Intel Corporation

    Inventor： Aaron LILAK ,  Patrick MORROW ,  Sayed HASAN

    IPC: H01L27/11556 ,  H01L27/11519 ,  H03K19/23

    Abstract: A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.

    TRANSISTORS STACKED ON FRONT-END P-TYPE TRANSISTORS
    60.
    发明申请
    TRANSISTORS STACKED ON FRONT-END P-TYPE TRANSISTORS 审中-公开

    公开(公告)号：US20200006388A1

    公开(公告)日：2020-01-02

    申请号：US16024696

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Gilbert DEWEY ,  Patrick MORROW ,  Aaron LILAK ,  Willy RACHMADY ,  Anh PHAN ,  Ehren MANNEBACH ,  Hui Jae YOO ,  Abhishek SHARMA ,  Van H. LE ,  Cheng-Ying HUANG

    IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8258

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

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