公开(公告)号：US10373893B2

公开(公告)日：2019-08-06

申请号：US15640406

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Aditya S. Vaidya ,  Ravindranath V. Mahajan ,  Digvijay A. Raorane ,  Paul R. Start

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/16

Abstract: An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.

公开(公告)号：US20170287831A1

公开(公告)日：2017-10-05

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US09548410B2

公开(公告)日：2017-01-17

申请号：US13717186

申请日：2012-12-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Brian S. Doyle ,  Ravindranath V. Mahajan

IPC: H01L31/048 ,  H01L27/30 ,  H02S20/26

CPC classification number: H01L31/0488 ,  H01L27/301 ,  H02S20/26 ,  Y02B10/10 ,  Y02E10/50

Abstract: An apparatus for collecting solar energy, including a first panel, wherein the first panel allows at least 50% of incident light having a wavelength in the range of 1 nm to 1,500 nm to pass through said panel and a second panel, wherein the second panel allows at least 50% of incident light having a wavelength in the range of 410 nm to 650 nm to pass through said panel. A photovoltaic cell is disposed between the first panel and second panel, which includes a first electrode disposed adjacent to the first panel, a second electrode disposed adjacent to the second panel, a photovoltaic component contacting the first and second electrodes. The photovoltaic component absorbs at least 50% of light having a wavelength in one of the following ranges: greater than 650 nm, less than 410 nm and combinations thereof.

Abstract translation: 一种用于收集太阳能的装置，包括第一面板，其中所述第一面板允许波长在1nm至1,500nm范围内的至少50％的入射光通过所述面板和第二面板，其中所述第二面板 允许波长在410nm至650nm范围内的至少50％的入射光通过所述面板。 光伏电池设置在第一面板和第二面板之间，其包括邻近第一面板设置的第一电极，邻近第二面板设置的第二电极，与第一和第二电极接触的光伏组件。 光伏组件吸收至少50％的具有以下范围之一的波长的光：大于650nm，小于410nm及其组合。

公开(公告)号：US20160181207A1

公开(公告)日：2016-06-23

申请号：US15055120

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  John S. Guzek ,  Adel A. Elsherbini ,  Nitin Ashok Deshpande

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/568 ,  H01L24/16 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/81

Abstract: An electromagnetic interference shield is described for semiconductor chip packages. In some embodiments, a mold compound is formed over a semiconductor die, the die being over a front side redistribution layer on a side opposite the mold compound, the redistribution layer extending past the die and the mold compound extending around the die to contact the redistribution layer. A plurality of vias are formed in the mold compound vertically toward the redistribution layer, the vias being outside of the die, wherein the bottoms of the vias are over a ground layer of the front side redistribution layer. A continuous conductive shielding film is applied over the mold compound and into the vias, wherein the shielding film in some of the vias directly connects to the ground layer and wherein the shielding film in some of the vias does not directly connect to the ground layer, the redistribution layer connecting the metal film to an external ground so that the vias form a shield.

Abstract translation: 半导体芯片封装描述了电磁干扰屏蔽。 在一些实施例中，在半导体管芯上形成模具化合物，模具位于与模具化合物相对的一侧上的正面再分配层上，再分配层延伸超过模具，并且模具化合物围绕模具延伸以接触再分布 层。 多个通孔在模具化合物中垂直地朝向再分布层形成，通孔在模具外部，其中通孔的底部在正面再分布层的接地层之上。 将连续导电屏蔽膜施加到模具化合物上并穿过通孔，其中一些通孔中的屏蔽膜直接连接到接地层，并且其中一些通孔中的屏蔽膜不直接连接到接地层， 再分配层将金属膜连接到外部地面，使得通孔形成屏蔽。

公开(公告)号：US09118188B2

公开(公告)日：2015-08-25

申请号：US13716376

申请日：2012-12-17

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Aleksandar Aleksov ,  Ravindranath V. Mahajan

IPC: H02J7/00 ,  H02J7/02

CPC classification number: H02J7/0004 ,  H02J7/0013 ,  H02J7/0042 ,  H02J7/0044 ,  H02J7/025 ,  H02J50/00 ,  H02J50/10 ,  H02J50/12 ,  H02J50/40 ,  H02J50/70 ,  H02J50/80 ,  Y02B40/90 ,  Y02E60/12

Abstract: A wireless charging system includes a microelectronic package (110) containing a system on chip (120) (an SoC), an energy transfer unit (140), and a software protocol (127). The SoC includes a processing device (121), a memory device (122) coupled to the processing device, and a communications device (123) coupled to the processing device and the memory device. The communications device is capable of communicating wirelessly with an external electronic device (130). The energy transfer unit is capable of transferring energy to the external electronic device. The software protocol is implemented in the memory device and is capable of detecting a charging profile of the external electronic device and capable of adjusting a parameter of the energy transfer unit according to a requirement of the charging profile.

Abstract translation: 一种无线充电系统包括一个包含片上系统（SoC），能量传输单元（140）和软件协议（127）的微电子封装（110）。 SoC包括处理设备（121），耦合到处理设备的存储设备（122）以及耦合到处理设备和存储设备的通信设备（123）。 通信设备能够与外部电子设备（130）进行无线通信。 能量传递单元能够将能量传递到外部电子设备。 软件协议在存储装置中实现，能够检测外部电子装置的充电曲线，并且能够根据充电曲线的要求调整能量转移单元的参数。