公开(公告)号：US20220140074A1

公开(公告)日：2022-05-05

申请号：US17578891

申请日：2022-01-19

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.

公开(公告)号：US11127815B2

公开(公告)日：2021-09-21

申请号：US16398987

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a fin structure having a circular cylindrical shape, and including a first recess formed on a first side of the fin structure and a second recess formed on a second side of the fin structure opposite the first side, an inner gate formed inside the fin structure, and an inner gate insulating layer formed between the inner gate and an inner surface of the fin structure.

公开(公告)号：US10985025B2

公开(公告)日：2021-04-20

申请号：US16173331

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/033 ,  H01L29/66

Abstract: Methods for forming semiconductor fins include forming a protective layer around a base of a hardmask fin on an underlying semiconductor layer. A portion of the hardmask fin is etched away with an etch that is selective to the protective layer. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US10886271B2

公开(公告)日：2021-01-05

申请号：US16040033

申请日：2018-07-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Sean Teehan

IPC: H01L27/092 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/08 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L29/165

Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.

公开(公告)号：US10833190B2

公开(公告)日：2020-11-10

申请号：US16516477

申请日：2019-07-19

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H03K17/687 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

公开(公告)号：US10790393B2

公开(公告)日：2020-09-29

申请号：US16267618

申请日：2019-02-05

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).

公开(公告)号：US20200135570A1

公开(公告)日：2020-04-30

申请号：US16173378

申请日：2018-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Eric R. Miller ,  Stuart A. Sieg ,  Yann Mignot ,  Indira Seshadri ,  Christopher J. Waskiewicz

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/033 ,  H01L27/088 ,  H01L29/66

Abstract: Methods for forming semiconductor fins include forming a sacrificial semiconductor structure around a hardmask fin on an underlying semiconductor layer. A first etch is performed that partially etches away a portion of the hardmask fin and the sacrificial semiconductor structure with a first etch chemistry. A second etch is performed that etches away remaining material of the portion of the hardmask fin and partially etches remaining material of the sacrificial semiconductor structure with a second etch chemistry. A semiconductor fin is etched from the semiconductor layer using the etched hardmask fin as a mask.

公开(公告)号：US10269931B2

公开(公告)日：2019-04-23

申请号：US15622769

申请日：2017-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/308

Abstract: Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.

公开(公告)号：US10256239B2

公开(公告)日：2019-04-09

申请号：US15296651

申请日：2016-10-18

Applicant: International Business Machines Corporation

Inventor： Balasubramanian Pranatharthiharan ,  Eric R. Miller ,  Soon-Cheon Seo ,  John R. Sporre

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L27/02 ,  H01L21/311

Abstract: A method of forming a semiconductor structure includes depositing a spacer material over a top surface of a substrate and two or more spaced-apart gates formed on the top surface of the substrate. The method also includes depositing a sacrificial liner over the spacer material and etching the sacrificial liner and the spacer material to expose portions of the top surface of the substrate between the two or more spaced-apart gates. The method further includes removing the sacrificial liner such that remaining spacer material forms two or more spacers between the two or more spaced-apart gates, each of the spacers including a first portion proximate the top surface of the substrate having a first width and a second portion above the first portion with a second width smaller than the first width.

公开(公告)号：US10249762B2

公开(公告)日：2019-04-02

申请号：US15938367

申请日：2018-03-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/417 ,  H01L29/775 ,  H01L29/78

Abstract: A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.