公开(公告)号：US20240186391A1

公开(公告)日：2024-06-06

申请号：US18062034

申请日：2022-12-06

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Sung Dae Suk ,  Ruilong Xie ,  Christopher J. Waskiewicz ,  Veeraraghavan S. Basker

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor structure includes a first gate-all-around device disposed on a first region of a substrate and a second gate-all-around device disposed on a second region of the substrate. The first gate-all-around device includes a first metal gate stack surrounding a first channel layer. The first metal gate stack is separated from a first source/drain region by a dielectric inner spacer disposed on opposite sides of the first metal gate stack. The second gate-all-around device includes a second metal gate stack surrounding a second channel layer. The second metal gate stack is separated from a second source/drain region by an epitaxial layer disposed on opposite sides of the second metal gate stack.

公开(公告)号：US20230187442A1

公开(公告)日：2023-06-15

申请号：US17551950

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Christopher J. Waskiewicz ,  Yann Mignot ,  Jeffrey C. Shearer ,  Hemanth Jagannathan

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823418

Abstract: A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source/drain region beneath the at least one vertical fin, a top source/drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source/drain region and first and second contact spacers disposed on each side of the contact.

公开(公告)号：US20230086785A1

公开(公告)日：2023-03-23

申请号：US17482504

申请日：2021-09-23

Applicant: International Business Machines Corporation

Inventor： Andrew Gaul ,  CHANRO PARK ,  Julien Frougier ,  Ruilong Xie ,  Andrew M. Greene ,  Christopher J. Waskiewicz

IPC: H01L27/092 ,  H01L21/8238

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide metal gate N/P boundary control in an integrated circuit (IC) using an active gate cut and recess processing scheme. In a non-limiting embodiment of the invention, a gate cut is formed in an N/P boundary between an n-type field effect transistor (FET) and a p-type FET. A first portion of a first work function metal is removed over a channel region of the n-type FET. The gate cut prevents etching a second portion of the first work function metal. The first portion of the first work function metal is replaced with a second work function metal. The gate cut is recessed, and a conductive region is formed on the recessed surface of the gate cut. The conductive region provides electrical continuity across the N/P boundary.

公开(公告)号：US11205723B2

公开(公告)日：2021-12-21

申请号：US16454561

申请日：2019-06-27

Applicant: International Business Machines Corporation

Inventor： Ardasheir Rahman ,  Brent Anderson ,  Junli Wang ,  Stuart Sieg ,  Christopher J. Waskiewicz

IPC: H01L29/06 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain.

公开(公告)号：US20210351073A1

公开(公告)日：2021-11-11

申请号：US16867757

申请日：2020-05-06

Applicant: International Business Machines Corporation

Inventor： Jennifer Fullam ,  Su Chen Fan ,  Christopher J. Waskiewicz ,  Muthumanickam Sankarapandian

IPC: H01L21/768

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

公开(公告)号：US20210313229A1

公开(公告)日：2021-10-07

申请号：US16839863

申请日：2020-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Christopher J. Waskiewicz ,  Kangguo Cheng ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a base structure including a first interlayer dielectric (ILD) layer and a contact including a conductive liner disposed along a conductive core, a conductive plug disposed on the conductive liner between the conductive core and the first ILD layer to a height of the base structure, and a metallization level including a conductive line and a self-aligned via underneath the conductive line disposed on the contact and the conductive plug. The conductive plug protects underlying material and increases connectivity between the self-aligned via and the contact that was reduced due to misalignment.

公开(公告)号：US10892336B2

公开(公告)日：2021-01-12

申请号：US16571256

申请日：2019-09-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Christopher J. Waskiewicz ,  Alexander Reznicek ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.

公开(公告)号：US20200075746A1

公开(公告)日：2020-03-05

申请号：US16117106

申请日：2018-08-30

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Su Chen Fan ,  Hari Prasad Amanapu ,  Hemanth Jagannathan

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08

Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.

公开(公告)号：US10461172B2

公开(公告)日：2019-10-29

申请号：US15850585

申请日：2017-12-21

Applicant: International Business Machines Corporation

Inventor： Christopher J. Waskiewicz ,  Hemanth Jagannathan ,  Yann Mignot ,  Stuart A. Sieg

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/40 ,  H01L21/311

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.

公开(公告)号：US10453793B2

公开(公告)日：2019-10-22

申请号：US16053282

申请日：2018-08-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Christopher J. Penny ,  Christopher J. Waskiewicz

IPC: H01L21/00 ,  H01L23/525 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.