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    Apparatus and method for reducing propagation delay in a conductor
    51.
    发明申请
    Apparatus and method for reducing propagation delay in a conductor 审中-公开
    减少导体传播延迟的装置和方法

    公开(公告)号：US20090206946A1

    公开(公告)日：2009-08-20

    申请号：US12378073

    申请日：2009-02-11

    Applicant: James Brady ,  Duane Giles Laurent

    Inventor： James Brady ,  Duane Giles Laurent

    IPC: H01P1/10

    CPC classification number: H01L23/5225 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An apparatus and method is provided that reduces the propagation delay in a conductor carrying an electrical signal from a first area of a circuit to a second area of the circuit. The conductor is fabricated to include a first conductor extending from the first area to the second area. The conductor also includes a second conductor extending substantially parallel and along the first conductor and electrically connected to the first conductor. A third and additional conductors may also be used which extend substantially parallel and along the first conductor and are electrically connected to the first conductor. The additional second conductor (and any additional conductors) reduces the capacitance of the conductor thereby reducing the propagation delay in the conductor (increasing the speed of the signal). The additional conductor(s) effectively “shield” the first conductor from some capacitance that the first conductor would normally “see” without the use of such additional conductors.

    Abstract translation: 提供了一种装置和方法，其减少了将电信号从电路的第一区域传递到电路的第二区域的导体中的传播延迟。 导体被制造成包括从第一区域延伸到第二区域的第一导体。 导体还包括基本上平行且沿着第一导体延伸并电连接到第一导体的第二导体。 还可以使用第三和附加导体，其基本上平行延伸并且沿着第一导体延伸并且电连接到第一导体。 额外的第二导体（和任何附加导体）减小了导体的电容，从而减少了导体中的传播延迟（增加了信号的速度）。 附加导体有效地“屏蔽”第一导体不受第一导体通常“看到”的一些电容，而不使用这种附加导体。

    Variable boost voltage row driver circuit and method, and memory device and system including same
    53.
    发明授权
    Variable boost voltage row driver circuit and method, and memory device and system including same 有权
    可变升压电压行驱动电路和方法，以及包括其的存储器件和系统

    公开(公告)号：US07085190B2

    公开(公告)日：2006-08-01

    申请号：US10944498

    申请日：2004-09-16

    Applicant: James Leon Worley ,  James Brady

    Inventor： James Leon Worley ,  James Brady

    IPC: G11C8/00

    CPC classification number: G11C8/08 ,  G11C11/4085

    Abstract: A row driver circuit receives a supply voltage and operates to develop a boosted voltage having a magnitude that is equal to the sum of an incremental boost voltage and a magnitude of the supply voltage. The magnitude of the incremental boost voltage is a function of the magnitude of the supply voltage to maintain the boosted voltage at an approximately constant value independent of variations in the supply voltage. A method of generating a boosted voltage includes detecting a value of a supply voltage, generating an incremental boost voltage having a value that is a function of the detected supply voltage, and adding the generated incremental boost voltage to the supply voltage to generate the boosted voltage.

    Abstract translation: 行驱动器电路接收电源电压并且操作以产生具有等于增量升压电压和电源电压幅度之和的幅度的升压电压。 增量升压电压的大小是电源电压幅度的函数，以将升压电压保持在大致恒定值，与电源电压的变化无关。 产生升压电压的方法包括检测电源电压的值，产生具有作为所检测的电源电压的函数的值的增量升压电压，以及将所产生的增量升压电压与电源电压相加以产生升压电压 。

    Particle detection system
    55.
    发明申请
    Particle detection system 审中-公开
    粒子检测系统

    公开(公告)号：US20050024641A1

    公开(公告)日：2005-02-03

    申请号：US10927671

    申请日：2004-08-27

    Applicant: Richard DeFreez ,  James Brady ,  Kenneth Girvin

    Inventor： Richard DeFreez ,  James Brady ,  Kenneth Girvin

    IPC: G01N15/14 ,  G01N21/53 ,  G01N21/00

    CPC classification number: G01N21/53 ,  G01N15/1429 ,  G01N15/1459 ,  G01N2015/1402

    Abstract: A particle detection system exhibits an increased ability to detect the presence of submicron diameter particles and to distinguish between noise and pulse output signals generated by small diameter particles on which a light beam is incident. This increased ability results from the incorporation of a light reflector, a pair of detector elements that detect correlated portions of the light beam that have been scattered in multiple directions, and a coincidence circuit that determines whether each detector element in the pair concurrently generates a pulse output signal exceeding a predetermined threshold. Sample particles are counted only when both detector elements concurrently detect scattered light components.

    Abstract translation: 颗粒检测系统表现出增加的检测亚微米直径颗粒的存在的能力，并且区分由光束入射的小直径颗粒产生的噪声和脉冲输出信号。 这种增加的能力来自于结合光反射器，检测已经在多个方向上散射的光束的相关部分的一对检测器元件，以及确定该对中的每个检测器元件是否同时产生脉冲的符合电路 输出信号超过预定阈值。 只有当两个检测器元件同时检测散射光分量时，才对样品颗粒进行计数。

    Redundant circuit and method for replacing defective memory cells in a memory device
    56.
    发明授权
    Redundant circuit and method for replacing defective memory cells in a memory device 有权

    公开(公告)号：US06535436B2

    公开(公告)日：2003-03-18

    申请号：US09790370

    申请日：2001-02-21

    Applicant: James Brady

    Inventor： James Brady

    IPC: G11C700

    CPC classification number: G11C29/848 ,  G11C8/10

    Abstract: A memory device having redundancy is disclosed. The memory device includes an array of memory cells organized into rows and columns of memory cells, each row of memory cells including a plurality of addressable memory cells and redundant memory cells, the array of memory cells including row lines and column lines, each row line being coupled to memory cells in a distinct row of memory cells, each column line being coupled to memory cells in a distinct column of memory cells, and column input/output lines. The memory device further includes a redundancy circuitry for selectively coupling column lines to column input/output lines of the array of memory cells and selectively decoupling at least one column line from the column input/output lines, based upon an address value received by the memory device during a memory access operation.

    Method of peritoneal dialysis
    57.
    发明授权
    Method of peritoneal dialysis 有权
    腹膜透析法

    公开(公告)号：US06527735B1

    公开(公告)日：2003-03-04

    申请号：US09560312

    申请日：2000-04-27

    Applicant: Vadim Davankov ,  James Brady ,  Nathan Levin

    Inventor： Vadim Davankov ,  James Brady ,  Nathan Levin

    IPC: B01J2026

    CPC classification number: B01J20/261 ,  A61M1/1696 ,  A61M1/28 ,  A61M1/287 ,  A61M1/3479 ,  A61M1/3486 ,  B01J20/26 ,  B01J20/267 ,  B01J20/28078 ,  B01J20/28083 ,  B01J20/28095

    Abstract: A method of peritoneal dialysis includes introducing a dialysis solution into a peritoneal cavity; allowing the dialysis solution to dwell in the peritoneal cavity for a period of time to provide diffusion through an inner lining of an abdominal cavity with exchange of components between a microcirculation of a peritoneum and a dialysis fluid; withdrawing the dialysis solution from the peritoneal cavity with toxins; passing the dialysis solution with toxins through an absorbent polymeric material which has a size, shape, and structure selected so as to remove the toxins in a molecular range of 300-30,000 Dalton from the spent dialysis solution; and returning the thusly purified peritoneal dialysis solution to the patient.

    Abstract translation: 腹膜透析的方法包括将透析溶液引入腹膜腔; 允许透析溶液在腹膜腔中停留一段时间，以通过腹膜的内部衬垫与腹膜的微循环与透析液之间的交换成分提供扩散; 用毒素从腹腔抽出透析溶液; 通过吸收性聚合物材料使透析溶液通过吸收性聚合物材料，该吸收性聚合物材料具有选择的尺寸，形状和结构，以便从废透析溶液中除去300-30,000道尔顿分子范围内的毒素; 并将如此纯化的腹膜透析溶液返回到患者体内。

    Method and apparatus for testing random access memory devices
    58.
    发明授权
    Method and apparatus for testing random access memory devices 有权
    用于测试随机存取存储器件的方法和装置

    公开(公告)号：US06185138B2

    公开(公告)日：2001-02-06

    申请号：US09434826

    申请日：1999-11-05

    Applicant: James Brady

    Inventor： James Brady

    IPC: G11C700

    CPC classification number: G11C29/34

    Abstract: A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

    Abstract translation: 一种用于测试随机存取存储器件的方法和装置，例如嵌入集成电路芯片内的动态随机存取存储器件。 该装置包括一行或多行晶体管，每行晶体管连接到存储器件的位线对和数据线。 通过将数据线驱动到预定电压电平并接通晶体管列中的晶体管，将数据放置在位线上。 放置在位线上的数据形成可以随后写入任何一行存储器单元的测试图案。 通过以这种方式直接控制存储器件的位线，测试图案可以快速且容易地存储在存储器件中用于其功能验证。

    Method and apparatus for testing random access memory devices
    59.
    发明授权
    Method and apparatus for testing random access memory devices 失效
    用于测试随机存取存储器件的方法和装置

    公开(公告)号：US6018484A

    公开(公告)日：2000-01-25

    申请号：US183591

    申请日：1998-10-30

    Applicant: James Brady

    Inventor： James Brady

    IPC: G11C11/401 ,  G11C29/34 ,  H01L21/822 ,  H01L27/04 ,  G11C7/00

    CPC classification number: G11C29/34

    Abstract: A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

    Abstract translation: 一种用于测试随机存取存储器件的方法和装置，例如嵌入集成电路芯片内的动态随机存取存储器件。 该装置包括一行或多行晶体管，每行晶体管连接到存储器件的位线对和数据线。 通过将数据线驱动到预定电压电平并接通晶体管列中的晶体管，将数据放置在位线上。 放置在位线上的数据形成可以随后写入任何一行存储器单元的测试图案。 通过以这种方式直接控制存储器件的位线，测试图案可以快速且容易地存储在存储器件中用于其功能验证。

    Method and apparatus for bit line recovery in dynamic random access memory
    60.
    发明授权
    Method and apparatus for bit line recovery in dynamic random access memory 有权
    用于动态随机存取存储器中位线恢复的方法和装置

    公开(公告)号：US5963485A

    公开(公告)日：1999-10-05

    申请号：US136695

    申请日：1998-08-19

    Applicant: James Brady ,  James L. Worley

    Inventor： James Brady ,  James L. Worley

    IPC: G11C11/409 ,  G11C7/12 ,  G11C7/00

    CPC classification number: G11C7/12

    Abstract: A bit line recovery circuit for random access memory. The circuit includes a pair of pull-up devices, each of which is connected to a bit line of a bit line pair. Pass gates are disposed between a sense amplifier and the bit lines. The pull-up devices are cross-coupled such that the gate node of the pull-up devices are connected to the sense amplifier on the opposed side of the pass gates in order to rapidly turn on the appropriate pull-up device following a memory cell read operation.

    Abstract translation: 一种用于随机存取存储器的位线恢复电路。 该电路包括一对上拉装置，每个上拉装置连接到位线对的位线。 传输门设置在读出放大器和位线之间。 上拉器件交叉耦合，使得上拉器件的栅极节点连接到通孔的相对侧上的读出放大器，以便快速接通存储器单元之后的适当的上拉器件 读操作。

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