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64 条记录 (耗时 0.023 秒)

    Self-protected drain-extended metal-oxide-semiconductor transistor
    52.
    发明授权
    Self-protected drain-extended metal-oxide-semiconductor transistor 有权
    自保护漏极扩展金属氧化物半导体晶体管

    公开(公告)号：US09058995B2

    公开(公告)日：2015-06-16

    申请号：US13440514

    申请日：2012-04-05

    申请人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

    发明人： Robert J. Gauthier, Jr. ,  Junjun Li ,  Alain Loiseau

    IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L27/02 ,  H01L29/74 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06

    CPC分类号： H01L27/027 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/7436 ,  H01L29/7824 ,  H01L29/7835

    摘要： Device structures, design structures, and fabrication methods for a drain-extended metal-oxide-semiconductor (DEMOS) transistor. A first well of a first conductivity type and a second well of a second conductivity type are formed in a device region. The first and second wells are juxtaposed to define a p-n junction. A first doped region of the first conductivity type and a doped region of the second conductivity type are in the first well. The first doped region of the first conductivity type is separated from the second well by a first portion of the first well. The doped region of the second conductivity type is separated from the second well by a second portion of the first well. A second doped region of the first conductivity type, which is in the second well, is separated by a portion of the second well from the first and second portions of the first well.

    摘要翻译： 漏极延伸金属氧化物半导体（DEMOS）晶体管的器件结构，设计结构和制造方法。 第一导电类型的第一阱和第二导电类型的第二阱形成在器件区域中。 第一和第二井并列以定义p-n结。 第一导电类型的第一掺杂区域和第二导电类型的掺杂区域位于第一阱中。 第一导电类型的第一掺杂区域与第一阱的第一部分与第二阱分离。 第二导电类型的掺杂区域与第一阱的第二部分与第二阱分离。 在第二阱中的第一导电类型的第二掺杂区域由第一阱的第一和第二部分的第二阱的一部分分开。

    Optimizing voltage on a power plane using a networked voltage regulation module array
    54.
    发明授权
    Optimizing voltage on a power plane using a networked voltage regulation module array 失效
    使用网络电压调节模块阵列优化电源平面上的电压

    公开(公告)号：US08341434B2

    公开(公告)日：2012-12-25

    申请号：US12037743

    申请日：2008-02-26

    申请人： Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  Norman J. Rohrer

    发明人： Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  Norman J. Rohrer

    IPC分类号： G06F1/00

    CPC分类号： G06F1/26

    摘要： A method, system, and computer program for using an array of networked 3D voltage regulation modules (VRMs) to optimize power usage by components on a voltage island in real time is presented. The networked VRM devices work in parallel to supply adequate power to connected voltage islands, and to supplement other VRMs in the system that may require additional power in the case of a critical event.

    摘要翻译： 提出了一种使用网络化的三维电压调节模块阵列（VRM）来实时优化电压岛上部件功率使用的方法，系统和计算机程序。 联网的VRM设备并行工作，为连接的电压岛提供足够的电力，并补充系统中可能需要额外功率的重要事件的其他VRM。

    PREDOPED TRANSFER GATE FOR A CMOS IMAGE SENSOR
    55.
    发明申请
    PREDOPED TRANSFER GATE FOR A CMOS IMAGE SENSOR 有权
    CMOS图像传感器的预置转移门

    公开(公告)号：US20090035886A1

    公开(公告)日：2009-02-05

    申请号：US11864713

    申请日：2007-09-28

    申请人： John Ellis-Monaghan ,  Jeffrey B. Johnson ,  Alain Loiseau

    发明人： John Ellis-Monaghan ,  Jeffrey B. Johnson ,  Alain Loiseau

    IPC分类号： H01L21/336

    CPC分类号： H01L27/14601 ,  H01L27/14612 ,  H01L27/14689

    摘要： A novel CMOS image sensor Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, a CMOS image sensor APS cell having a predoped transfer gate is formed that avoids the variations of Vt as a result of subsequent manufacturing steps. According to the preferred embodiment of the invention, the CMOS image sensor APS cell structure includes a doped p-type pinning layer and an n-type doped gate. There is additionally provided a method of forming the CMOS image sensor APS cell having a predoped transfer gate and a doped pinning layer. The predoped transfer gate prevents part of the gate from becoming p-type doped.

    摘要翻译： 一种新颖的CMOS图像传感器有源像素传感器（APS）单元结构及其制造方法。 特别地，形成具有预制传输门的CMOS图像传感器APS单元，其避免了作为后续制造步骤的结果的Vt的变化。 根据本发明的优选实施例，CMOS图像传感器APS单元结构包括掺杂的p型钉扎层和n型掺杂栅极。 还提供了一种形成具有预制传输栅极和掺杂钉扎层的CMOS图像传感器APS单元的方法。 预制传输门防止栅极的一部分变成p型掺杂。

    High Dynamic Range Imaging Cell With Electronic Shutter Extensions
    57.
    发明申请
    High Dynamic Range Imaging Cell With Electronic Shutter Extensions 有权
    高动态范围成像电池与电子快门扩展

    公开(公告)号：US20080224186A1

    公开(公告)日：2008-09-18

    申请号：US11687245

    申请日：2007-03-16

    申请人： John J Ellis-Monaghan ,  Alain Loiseau ,  Kirk D. Peterson

    发明人： John J Ellis-Monaghan ,  Alain Loiseau ,  Kirk D. Peterson

    IPC分类号： H01L31/113

    CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H04N5/3559 ,  H04N5/37452

    摘要： A pixel sensor cell of improved dynamic range comprises a coupling transistor that couples a capacitor device to a photosensing region (e.g., photodiode) of the pixel cell, the photodiode being coupled to a transfer gate and one terminal of the coupling transistor. In operation, the additional capacitance is coupled to the pixel cell photodiode when the voltage on the photodiode is drawn down to the substrate potential. Thus, the added capacitance is only connected to the imager cell when the cell is nearing its charge capacity. Otherwise, the cell has a low capacitance and low leakage. In an additional embodiment, a terminal of the capacitor is coupled to a “pulsed” supply voltage signal that enables substantially full depletion of stored charge from the capacitor to the photosensing region during a read out operation of the pixel sensor cell. In various embodiments, the locations of the added capacitance and photodiode may be interchanged with respect to the coupling transistor. In addition, the added capacitor of the pixel sensor cell allows for a global shutter operation.

    摘要翻译： 改进的动态范围的像素传感器单元包括将电容器器件耦合到像素单元的光敏区域（例如光电二极管）的耦合晶体管，光电二极管耦合到传输门和耦合晶体管的一个端子。 在操作中，当光电二极管上的电压向下拉到衬底电位时，附加电容耦合到像素单元光电二极管。 因此，当电池接近其充电容量时，所添加的电容仅连接到成像器单元。 否则，电池具有低电容和低泄漏。 在另外的实施例中，电容器的端子耦合到“脉冲”电源电压信号，其在像素传感器单元的读出操作期间使存储的电荷从电容器充分耗尽。 在各种实施例中，增加的电容和光电二极管的位置可以相对于耦合晶体管互换。 此外，像素传感器单元的附加电容允许全局快门操作。

    Voltage Identifier Sorting
    58.
    发明申请
    Voltage Identifier Sorting 有权
    电压标识符排序

    公开(公告)号：US20080168318A1

    公开(公告)日：2008-07-10

    申请号：US11621766

    申请日：2007-01-10

    申请人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

    发明人： Jonathan J. DeMent ,  Sang H. Dhong ,  Gilles Gervais ,  Alain Loiseau ,  Kirk D. Peterson ,  John L. Sinchak

    IPC分类号： G01R31/30 ,  G06F11/00

    CPC分类号： G01R31/3004 ,  G01R31/31721 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A voltage identifier (VID) sorting system is provided that optimizes processor power and operating voltage guardband at a constant processor frequency. The VID sorting system determines a voltage versus current curve for the processor. The VID sorting system then uses the voltage versus current characteristics to calculate the power for each VID to determine an acceptable range of VIDs within the maximum power criteria. The VID sorting system then tests VIDs in the range and selects a VID from the range to optimize for minimum power and/or maximum voltage guardband at a constant processor frequency.

    摘要翻译： 提供了一种电压标识符（VID）分类系统，其以恒定的处理器频率优化处理器功率和工作电压保护带。 VID分选系统确定处理器的电压与电流曲线。 然后，VID分选系统使用电压与电流特性来计算每个VID的功率，以确定最大功率标准内的VID的可接受范围。 VID分类系统然后测试该范围内的VID，并从该范围中选择一个VID，以在恒定的处理器频率下对最小功率和/或最大电压保护带进行优化。

    Method of adjusting buried resistor resistance
    59.
    发明授权
    Method of adjusting buried resistor resistance 有权
    调整埋电阻电阻的方法

    公开(公告)号：US07393701B2

    公开(公告)日：2008-07-01

    申请号：US11566887

    申请日：2006-12-05

    申请人： Douglas B. Hershberger ,  Alain Loiseau ,  Kirk D. Peterson ,  Robert M. Rassel

    发明人： Douglas B. Hershberger ,  Alain Loiseau ,  Kirk D. Peterson ,  Robert M. Rassel

    IPC分类号： H01L21/302 ,  H01L21/308

    CPC分类号： H01L22/20 ,  H01L22/14

    摘要： Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.

    摘要翻译： 公开了调整半导体中的埋入电阻的电阻的方法。 一方面，该方法包括使用硅化阻挡掩模来限定半导体中的掩埋电阻; 调整硅化阻挡掩模的尺寸以根据来自包括基本相似的掩埋电阻器的先前处理批次的测试数据来调整埋入电阻器的电阻; 并且在未被硅化阻挡掩模覆盖的区域上形成硅化物。 可以通过平衡用硅化物覆盖的电阻器与非硅化半导体的量来实现所需的总电阻来进行调整。 可以根据算法进行调整。

    METHOD OF ADJUSTING BURIED RESISTOR RESISTANCE
    60.
    发明申请
    METHOD OF ADJUSTING BURIED RESISTOR RESISTANCE 有权
    调整电阻电阻的方法

    公开(公告)号：US20080131980A1

    公开(公告)日：2008-06-05

    申请号：US11566887

    申请日：2006-12-05

    申请人： Douglas B. Hershberger ,  Alain Loiseau ,  Kirk D. Peterson ,  Robert M. Rassel

    发明人： Douglas B. Hershberger ,  Alain Loiseau ,  Kirk D. Peterson ,  Robert M. Rassel

    IPC分类号： H01L21/66 ,  G01R31/26

    CPC分类号： H01L22/20 ,  H01L22/14

    摘要： Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.

    摘要翻译： 公开了调整半导体中的埋入电阻的电阻的方法。 一方面，该方法包括使用硅化阻挡掩模来限定半导体中的掩埋电阻; 调整硅化阻挡掩模的尺寸以根据来自包括基本相似的掩埋电阻器的先前处理批次的测试数据来调整埋入电阻器的电阻; 并且在未被硅化阻挡掩模覆盖的区域上形成硅化物。 可以通过平衡用硅化物覆盖的电阻器与非硅化半导体的量来实现所需的总电阻来进行调整。 可以根据算法进行调整。