公开(公告)号：US20120113705A1

公开(公告)日：2012-05-10

申请号：US13348895

申请日：2012-01-12

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C5/06

CPC分类号： G11C7/1078 ,  G11C5/02 ,  G11C5/04 ,  G11C7/109 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2254 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01055

摘要： Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications in processor-based systems. More specifically, embodiments of the present invention include processor-based systems with volatile-memory having memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

摘要翻译： 本发明的实施例涉及用于基于处理器的系统中的存储器和存储器堆叠应用的可配置输入和/或输出。 更具体地，本发明的实施例包括具有易失性存储器的基于处理器的系统，其具有存储器件，存储器件包括具有被配置为通过特定信号启用的电路的管芯，被配置为接收特定信号的输入引脚和配置为 以选择性地从输入引脚指定电路的信号路径。

公开(公告)号：US20110103122A1

公开(公告)日：2011-05-05

申请号：US12986947

申请日：2011-01-07

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C5/04

CPC分类号： G06F13/1684 ,  G11C5/025 ,  G11C5/04

摘要： An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

摘要翻译： 装置和方法将存储器模块中的存储器件耦合到模块上的存储器集线器，使得从集线器传输到设备的信号具有大致相同的传播时间，而不管涉及哪个设备。 具体地，设备成对地布置在集线器周围，每对设备被定向成使得成对中的每个设备（例如数据总线信号）的功能信号组彼此相邻地定位在 模块。 这允许具有大致相同电特性的数据和控制地址总线在集线器和每个设备之间路由。 这种设备的物理布置允许模块的高速运行。 在一个示例中，集线器位于模块的中心，并且四个对设置在集线器周围的八个设备。

公开(公告)号：US20100257332A1

公开(公告)日：2010-10-07

申请号：US12820877

申请日：2010-06-22

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Jeffrey P. Wright ,  James S. Cullum

IPC分类号： G06F13/36 ,  G06F12/00

CPC分类号： G11C11/4096 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

摘要： A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.

摘要翻译： 一种用于对命令信号进行解码的系统和方法，该系统和方法包括一个命令解码器，该命令解码器经配置以产​​生内部控制信号，以根据命令信号和操作状态执行操作。 命令信号的相同组合可以根据操作状态请求不同的命令。 当存储器系统处于第一操作状态时，根据命令信号从第一组操作中选择命令，并且当存储器系统处于第二操作时根据命令信号从第二组操作中选择命令 州。

公开(公告)号：US07142461B2

公开(公告)日：2006-11-28

申请号：US10383939

申请日：2003-03-07

申请人： Jeffery W. Janzen

发明人： Jeffery W. Janzen

IPC分类号： G11C7/10

CPC分类号： G06F13/4086

摘要： A method and apparatus are provided for active termination control in a memory by a module register providing an active termination control signal to the memory. The module register monitors a system command bus for read and write commands. In response to detecting a read or write command, the module register generates an active termination control signal to the memory. The memory turns on active termination based on information programmed into one or more mode registers of the memory. The memory maintains the active termination in an on state for a predetermined time based on information programmed into one or more mode registers of the memory.

摘要翻译： 提供了一种方法和装置，用于通过模块寄存器向存储器中的主动终止控制提供活动终止控制信号给存储器。 模块寄存器监视系统命令总线以进行读写命令。 响应于检测到读或写命令，模块寄存器产生到存储器的有效终止控制信号。 存储器根据编程到存储器的一个或多个模式寄存器中的信息，开启有效终止。 存储器基于编程到存储器的一个或多个模式寄存器中的信息，将活动终止维持在接通状态达预定时间。

公开(公告)号：US06888719B1

公开(公告)日：2005-05-03

申请号：US10686864

申请日：2003-10-16

申请人： Jeffery W. Janzen ,  Christopher S. Johnson

发明人： Jeffery W. Janzen ,  Christopher S. Johnson

IPC分类号： G06F1/20 ,  H01L23/367 ,  H01L23/40 ,  H05K5/00 ,  H05K7/20

CPC分类号： H01L23/367 ,  H01L23/4093 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatuses for transferring heat from microelectronic device modules are disclosed. An apparatus in accordance with one embodiment of the invention can include first and second heat transfer portions positioned to face toward opposing faces of a microelectronic device module. Heat transfer fins having different length can extend away from at least one of the heat transfer portions. In one embodiment, the heat transfer fins can be integrally formed with other portions of the apparatus. In other embodiments, modules carrying the heat transfer devices can be mounted at an acute angle relative to a support structure (such as a PCB) so that heat transfer fins from one module can extend adjacent to the end region of the neighboring module. This arrangement can increase the rate at which heat is transferred away from the modules, and can increase the utilization of a limited heat transfer volume within a device, such as a computer.

摘要翻译： 公开了从微电子器件模块传递热量的方法和装置。 根据本发明的一个实施例的装置可以包括定位成面向微电子器件模块的相对面的第一和第二传热部分。 具有不同长度的传热翅片可以远离至少一个传热部分延伸。 在一个实施例中，传热翅片可以与设备的其它部分一体形成。 在其它实施例中，承载传热装置的模块可相对于支撑结构（例如PCB）以锐角安装，使得来自一个模块的传热散热片可以相邻于相邻模块的端部区域延伸。 这种布置可以增加热量从模块转移的速率，并且可以增加设备（例如计算机）内有限的传热体积的利用率。

公开(公告)号：US06851016B2

公开(公告)日：2005-02-01

申请号：US10720183

申请日：2003-11-25

申请人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

发明人： Jeffery W. Janzen ,  Brent Keeth ,  Kevin J. Ryan ,  Troy A. Manning ,  Brian Johnson

IPC分类号： G06F12/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.

摘要翻译： 在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。 本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统 读延迟。

公开(公告)号：US06847583B2

公开(公告)日：2005-01-25

申请号：US10778145

申请日：2004-02-17

申请人： Jeffery W. Janzen ,  Troy A. Manning ,  Chris G. Martin ,  Brent Keeth

发明人： Jeffery W. Janzen ,  Troy A. Manning ,  Chris G. Martin ,  Brent Keeth

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/1066 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409 ,  G11C2207/107 ,  G11C2207/2254 ,  G11C2207/2281

摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.

摘要翻译： 通过使用至少一个标志信号来使高速同步存储器子系统中的多个存储器件的读取等待时间被均衡。 标志信号具有等效信号传播特性的读时钟信号，从而自动补偿信号传播的影响。 在检测到标志信号之后，存储器件将以预定数量的时钟周期开始输出与先前接收到的读取命令相关联的数据。 对于每个标志信号，存储器控制器在系统初始化时确定在发出读取命令和发出标志信号以均衡系统读取延迟之间所需的延迟。 然后将延迟应用于在存储器系统的常规操作期间读取事务。

公开(公告)号：US06724666B2

公开(公告)日：2004-04-20

申请号：US10222798

申请日：2002-08-19

申请人： Jeffery W. Janzen ,  Troy A. Manning ,  Chris G. Martin ,  Brent Keeth

发明人： Jeffery W. Janzen ,  Troy A. Manning ,  Chris G. Martin ,  Brent Keeth

IPC分类号： G11C700

CPC分类号： G11C7/1066 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/409 ,  G11C2207/107 ,  G11C2207/2254 ,  G11C2207/2281

摘要： The read latency of a plurality of memory devices in a high speed synchronous memory subsystem is equalized through the use of at least one flag signal. The flag signal has equivalent signal propagation characteristics read clock signal, thereby automatically compensating for the effect of signal propagation. After detecting the flag signal, a memory device will begin outputting data associated with a previously received read command in a predetermined number of clock cycles. For each of the flag signal, the memory controller, at system initialization, determines the required delay between issuing a read command and issuing the flag signal to equalize the system read latencies. The delay(s) are then applied to read transactions during regular operation of the memory system.