公开(公告)号：US20110227606A1

公开(公告)日：2011-09-22

申请号：US13149168

申请日：2011-05-31

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03K19/0175 ,  H03K3/00

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US20080186056A1

公开(公告)日：2008-08-07

申请号：US11830831

申请日：2007-07-30

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen ,  Philip Pan

IPC分类号： H03K19/0175

CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

摘要翻译： 提供高速或低速灵活的输入和输出的方法和设备。 提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。 选择其中一个输入和输出电路，并取消选择其他电路。 高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。 低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。 这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

公开(公告)号：US20070236247A1

公开(公告)日：2007-10-11

申请号：US11381356

申请日：2006-05-02

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K17/16

CPC分类号： G11C7/1048 ,  G11C2207/2254 ,  H03H11/30 ,  H04L25/0278 ,  H04L25/0292

摘要： On-chip termination (OCT)calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.

摘要翻译： 提供使用OCT控制器在集成电路（IC）上支持输入/输出（IO）组的片上终止（OCT）校准技术。 OCT控制器使用共享并行总线或单独的并行总线校准IO组中的片上终端阻抗。 每个IO组中的多路复用器或选择逻辑根据选择信号选择来自OCT控制器的控制信号。 根据一些实施例，IC上的每个IO组可以从IC上的任何OCT控制器接收OCT控制信号。

公开(公告)号：US06970024B1

公开(公告)日：2005-11-29

申请号：US10786370

申请日：2004-02-24

申请人： Dirk Reese ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Gopinath Rangan ,  Xiaobao Wang

发明人： Dirk Reese ,  Tzung-Chin Chang ,  Chiakang Sung ,  Khai Nguyen ,  Gopinath Rangan ,  Xiaobao Wang

IPC分类号： H03K3/01 ,  H03K3/356 ,  H03K19/003

CPC分类号： H03K3/356113 ,  H03K19/00315

摘要： Circuits, methods, and apparatus for protecting devices in an output stage from over-voltage conditions caused by high supply and input voltages. Embodiments provide over-voltage protection that operates over a range of voltage levels, and that can be optimized for performance at different voltage levels. An exemplary embodiment of the present invention uses stacked devices to protect n and p-channel output devices from excess supply and input voltages. These stacked devices are biased by voltages received at their gates. These gate voltages vary as a function of supply voltage to maintain performance. Other embodiments of the present invention provide a body bias switch that generates a bias for the bulk of p-channel output devices. This bias tracks the higher of a supply or input voltage, such that parasitic drain-to-bulk diodes do not conduct. A switch may be provided that shorts the bulk connection to VCC under appropriate conditions.

摘要翻译： 用于保护输出级的器件免受由高电源和输入电压引起的过电压状态的电路，方法和装置。 实施例提供了在一定范围的电压电平上工作的过电压保护，并且可针对不同电压电平下的性能进行优化。 本发明的示例性实施例使用堆叠器件来保护n和p沟道输出器件免受过多的电源和输入电压的影响。 这些堆叠的器件被其栅极处接收的电压偏置。 这些栅极电压随着电源电压而变化，以保持性能。 本发明的其它实施例提供一种主体偏置开关，其产生用于大量p沟道输出装置的偏置。 该偏置跟踪电源或输入电压的较高，使得寄生漏极 - 体二极管不导通。 可以提供在适当条件下短路与VCC的大容量连接的开关。

公开(公告)号：US06400598B1

公开(公告)日：2002-06-04

申请号：US09843299

申请日：2001-04-25

申请人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

发明人： Khai Nguyen ,  Xiaobao Wang ,  In Whan Kim ,  Chiakang Sung ,  Richard G. Cliff ,  Joseph Huang ,  Bonnie I. Wang ,  Wayne Yeung

IPC分类号： G11C506

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784

摘要： A programmable logic device is equipped for low voltage differential signaling (“LVDS”) by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.

摘要翻译： 可编程逻辑器件通过在器件上提供LVDS输入缓冲器和/或LVDS输出缓冲器来配备低电压差分信号（“LVDS”）。 对于LVDS成对使用的设备上的I / O引脚可以单独用于其他类型的信令。 尽管由于温度，制造过程不一致以及电源变化而导致变化，LVDS缓冲器也可以提供良好的性能和满足LVDS规范。

公开(公告)号：US06346827B1

公开(公告)日：2002-02-12

申请号：US09366937

申请日：1999-08-04

申请人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

发明人： Wayne Yeung ,  Chiakang Sung ,  Myron W. Wong ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang ,  Joseph Huang ,  In Whan Kim

IPC分类号： H01L2500

CPC分类号： G11C5/147 ,  G11C5/066

摘要： A programmable input/output circuit for a programmable logic device input/output pin can be configured in a standard I/O mode, or in a reference voltage mode. The circuit includes a tristatable, but otherwise standard I/O buffer as well as a reference voltage clamp circuit. In reference voltage mode, the I/O circuit is tristated, and the reference voltage clamp circuit passes a reference voltage from the I/O pin to a reference voltage bus. In standard I/O mode, the I/O buffer is operational. The reference voltage clamp circuit isolates the I/O pin from the reference voltage bus and may include undervoltage and overvoltage protection to prevent disturbance of the reference voltage bus by an out-of-range I/O signal.

摘要翻译： 可编程逻辑器件输入/输出引脚的可编程输入/输出电路可以在标准I / O模式或参考电压模式下进行配置。 该电路包括可跟踪的标准I / O缓冲器以及参考电压钳位电路。 在参考电压模式下，I / O电路被三态化，参考电压钳位电路将参考电压从I / O引脚传递到参考电压总线。 在标准I / O模式下，I / O缓冲区可以运行。 参考电压钳位电路将I / O引脚与参考电压总线隔离，并可能包括欠压和过压保护，以防止参考电压总线受到超出范围I / O信号的干扰。

公开(公告)号：US08610462B1

公开(公告)日：2013-12-17

申请号：US13332730

申请日：2011-12-21

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen ,  Bonnie I. Wang

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03K3/00 ,  H03B1/00

CPC分类号： H03K3/356113

摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

摘要翻译： 公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。 具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。 电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。 当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

公开(公告)号：US08390315B1

公开(公告)日：2013-03-05

申请号：US13354780

申请日：2012-01-20

申请人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Joseph Huang ,  Khai Nguyen

IPC分类号： H03K19/013 ,  H03K17/16

CPC分类号： H03K19/01721 ,  H03K19/018571

摘要： Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.

摘要翻译： 公开了具有可配置的输入 - 输出电路来操作集成电路（IC）的电路和技术。 所公开的电路包括耦合到输出端子的单端输入 - 输出缓冲器。 单端输入 - 输出缓冲器可用于将输入信号作为输出信号发送到输出端。 用于锐化输出信号的第一边缘和第二边缘的预加重电路耦合在单端输入 - 输出缓冲器和输出端子之间。 当输入信号从第一逻辑电平切换到第二逻辑电平时，输出信号的第一边缘被锐化，而当输入信号从第二逻辑电平切换到第一逻辑电平时，输出信号的第二边沿被锐化。

公开(公告)号：US07994821B1

公开(公告)日：2011-08-09

申请号：US12753389

申请日：2010-04-02

申请人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Xiaobao Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K19/0175

CPC分类号： H03K3/356069

摘要： A level shifter circuit includes first and second transistors coupled in series and third and fourth transistors coupled in series. The fourth transistor is coupled to a first node between the first and the second transistors. The level shifter circuit also includes fifth and sixth transistors coupled in series and seventh and eighth transistors coupled in series. The eighth transistor is coupled to a second node between the fifth and the sixth transistors. The second and the eighth transistors receive a first input signal at control inputs. The fourth and the sixth transistors receive a second input signal at control inputs. The second input signal is inverted relative to the first input signal.

摘要翻译： 电平移位器电路包括串联耦合的第一和第二晶体管，以及串联耦合的第三和第四晶体管。 第四晶体管耦合到第一和第二晶体管之间的第一节点。 电平移位器电路还包括串联耦合的第五和第六晶体管，以及串联耦合的第七和第八晶体管。 第八晶体管耦合到第五和第六晶体管之间的第二节点。 第二和第八晶体管在控制输入端接收第一输入信号。 第四和第六晶体管在控制输入端接收第二输入信号。 第二输入信号相对于第一输入信号反相。

公开(公告)号：US07973553B1

公开(公告)日：2011-07-05

申请号：US12721759

申请日：2010-03-11

申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278

摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.

摘要翻译： 电路包括第一晶体管和比较器。 比较器比较参考信号和基于第一晶体管的导电状态的信号。 控制电路根据比较器的输出信号产生第一控制信号。 基于第一控制信号来确定第一晶体管的导通状态。 算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。 第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。