利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

82 条记录 (耗时 0.034 秒)

    Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications
    51.
    发明授权
    Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications 失效
    用于FeRAM器件应用的SiO2，Ti和In2 O3薄膜的选择性蚀刻工艺

    公开(公告)号：US07364665B2

    公开(公告)日：2008-04-29

    申请号：US10970885

    申请日：2004-10-21

    申请人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC分类号： H01L29/6684 ,  C23F4/00 ,  H01L21/28291 ,  H01L21/31116 ,  H01L21/32136

    摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.

    摘要翻译： 选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO 2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压， 约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。

    Multi-layered barrier metal thin films for Cu interconnect by ALCVD
    53.
    发明授权
    Multi-layered barrier metal thin films for Cu interconnect by ALCVD 有权

    公开(公告)号：US07015138B2

    公开(公告)日：2006-03-21

    申请号：US09819296

    申请日：2001-03-27

    申请人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

    摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

    Asymmetric memory cell
    55.
    发明授权
    Asymmetric memory cell 有权
    不对称记忆单元

    公开(公告)号：US06927074B2

    公开(公告)日：2005-08-09

    申请号：US10442627

    申请日：2003-05-21

    申请人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans

    发明人： Sheng Teng Hsu ,  Tingkai Li ,  David R. Evans

    IPC分类号： H01L27/10 ,  G11C11/15 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L21/00

    CPC分类号： G11C13/0007 ,  B82Y10/00 ,  G11C11/15 ,  G11C2213/31 ,  G11C2213/52 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147

    摘要： An asymmetric memory cell and method for forming an asymmetric memory cell are provided. The method comprises: forming a bottom electrode having a first area; forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode; forming a top electrode overlying the EPVR layer having a second area, less than the first area. In some aspects the second area is at least 20% smaller than the first area. The EPVR is a material such as colossal magnetoresistance (CMR), high temperature super conducting (HTSC), or perovskite metal oxide materials. The method further comprises: inducing an electric field between the electrodes; inducing current flow through the EPVR adjacent the top electrode; and, in response to inducing current flow through the EPVR adjacent the top electrode, modifying the resistance of the EPVR. Typically, the resistance is modified within the range of 100 ohms to 10 mega-ohms.

    摘要翻译： 提供了一种用于形成非对称存储单元的非对称存储单元和方法。 该方法包括：形成具有第一区域的底部电极; 形成覆盖底部电极的各种电阻（EPVR）材料的电脉冲; 形成覆盖在EPVR层上的顶部电极，其具有小于第一区域的第二区域。 在一些方面，第二区域比第一区域小至少20％。 EPVR是诸如巨磁阻（CMR），高温超导（HTSC）或钙钛矿金属氧化物材料的材料。 该方法还包括：在电极之间引入电场; 通过邻近顶部电极的EPVR引起电流流动; 并且响应于通过与顶部电极相邻的EPVR的电流流动，修改EPVR的电阻。 通常，电阻在100欧姆到10兆欧姆的范围内被修改。

    Copper metal precursor
    56.
    发明授权
    Copper metal precursor 失效
    铜金属前体

    公开(公告)号：US06764537B2

    公开(公告)日：2004-07-20

    申请号：US10453829

    申请日：2003-06-02

    申请人： Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： C23C1618

    CPC分类号： H01L21/28556 ,  C23C16/18

    摘要： A method for chemical vapor deposition of copper metal thin film on a substrate includes heating a substrate onto which the copper metal thin film is to be deposited in a chemical vapor deposition chamber; vaporizing a precursor containing the copper metal, wherein the precursor is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene; introducing the vaporized precursor into the chemical vapor deposition chamber adjacent the heated substrate; and condensing the vaporized precursor onto the substrate thereby depositing copper metal onto the substrate. A copper metal precursor for use in the chemical vapor deposition of a copper metal thin film is a compound of (&agr;-methylstyrene)Cu(I)(hfac), where hfac is hexafluoroacetylacetonate, and (hfac)Cu(I)L, where L is an alkene taken from the group of alkenes consisting of 1-pentene, 1-hexene and trimethylvinylsilane.

    摘要翻译： 铜基金属薄膜在基板上进行化学气相沉积的方法包括在化学气相沉积室中加热要沉积铜金属薄膜的基板; 蒸发含有铜金属的前体，其中前体是（α-甲基苯乙烯）Cu（I）（hfac）的化合物，其中hfac是六氟乙酰丙酮化物，和（hfac）Cu（I）L，其中L是烯烃; 将蒸发的前体引入与加热的基底相邻的化学气相沉积室; 并将蒸发的前体冷凝到基底上，从而将铜金属沉积到基底上。 用于铜金属薄膜的化学气相沉积的铜金属前体是（α-甲基苯乙烯）Cu（I）（hfac）的化合物，其中hfac是六氟乙酰丙酮化物，和（hfac）Cu（I）L，其中 L是从由1-戊烯，1-己烯和三甲基乙烯基硅烷组成的烯烃族中获得的烯烃。

    Ultra thin tungsten metal films used as adhesion promoter between barrier metals and copper
    57.
    发明授权
    Ultra thin tungsten metal films used as adhesion promoter between barrier metals and copper 有权
    超薄钨金属膜用作阻挡金属和铜之间的粘合促进剂

    公开(公告)号：US06716744B2

    公开(公告)日：2004-04-06

    申请号：US10140460

    申请日：2002-05-06

    申请人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： H01L214763

    CPC分类号： H01L21/76846 ,  H01L21/28556 ,  H01L21/28562 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of adhering copper thin film to a substrate in an integrated circuit structure includes preparing a substrate, including forming active regions and trenches for interconnect structures; depositing a metal barrier layer on the substrate; depositing an ultra thin film layer of tungsten over the barrier metal layer; depositing a copper thin film on the tungsten ultra thin film layer; removing excess copper and tungsten to the level of the metal barrier layer; and completing the integrated circuit structure. An integrated circuit having a copper interconnect therein formed over a layer of barrier metal includes a substrate, including active regions, vias and trenches for interconnect structures; a metal barrier layer formed on the substrate, wherein said metal barrier layer is taken from the group of materials consisting of Ta, TiN, TaN, TaSiN and TiSiN, and formed to a thickness of between about 5 nm to 10 nm; an ultra thin film layer of tungsten formed on the barrier metal layer, said tungsten ultra thin film layer having a thickness of between about 1 nm to 5 nm; and a copper thin film layer formed on the tungsten ultra thin film layer to a thickness sufficient to fill the vias and trenches.

    摘要翻译： 在集成电路结构中将铜薄膜粘合到基板上的方法包括制备基板，包括形成用于互连结构的有源区和沟槽; 在衬底上沉积金属阻挡层; 在所述阻挡金属层上沉积钨的超薄膜层; 在钨超薄膜层上沉积铜薄膜; 将过量的铜和钨去除到金属阻挡层的水平; 并完成集成电路结构。 在其上形成有铜互连的集成电路包括一个衬底，包括有源区，用于互连结构的通孔和沟槽; 形成在所述基板上的金属阻挡层，其中所述金属阻挡层取自由Ta，TiN，TaN，TaSiN和TiSiN组成的材料组，并形成为约5nm至10nm的厚度; 形成在所述阻挡金属层上的钨的超薄膜层，所述钨超薄膜层的厚度为约1nm至5nm; 以及形成在钨超薄膜层上的厚度足以填充通路和沟槽的厚度的铜薄膜层。

    Dual metal gate CMOS devices and method for making the same
    59.
    发明授权
    Dual metal gate CMOS devices and method for making the same 失效

    公开(公告)号：US06573134B2

    公开(公告)日：2003-06-03

    申请号：US09817834

    申请日：2001-03-27

    申请人： Yanjun Ma ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

    发明人： Yanjun Ma ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

    IPC分类号： H01L218238

    CPC分类号： H01L21/823842 ,  H01L27/092

    摘要： A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.