公开(公告)号：US07256429B2

公开(公告)日：2007-08-14

申请号：US11314222

申请日：2005-12-21

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

IPC分类号： H01L21/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

摘要翻译： 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。

公开(公告)号：US07094691B2

公开(公告)日：2006-08-22

申请号：US10410029

申请日：2003-04-09

申请人： Wei Pan ,  Robert Barrowcliff ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Robert Barrowcliff ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/76841 ,  C23C16/34

摘要： A method of forming a tungsten nitride thin film in an integrated circuit includes preparing a silicon substrate on a silicon wafer and placing the silicon wafer in a heatable chuck in a CVD vacuum chamber; placing a known quantity of a tungsten source in a variable-temperature bubbler to provide a gaseous tungsten source; setting the variable-temperature bubbler to a predetermined temperature; passing a carrier gas through the variable-temperature bubbler and carrying the gaseous tungsten source with the carrier gas into the CVD vacuum chamber; introducing a nitrogen-containing reactant gas into the CVD vacuum chamber; reacting the gaseous tungsten source and the nitrogen-containing reactant gas above the surface of the silicon wafer in a deposition process to deposit a WxNy thin film on the surface of the silicon wafer; and completing the integrated circuit containing the WxNy thin film.

摘要翻译： 在集成电路中形成氮化钨薄膜的方法包括在硅晶片上制备硅衬底，并将硅晶片放置在CVD真空室中的可加热卡盘中; 将已知量的钨源放置在可变温度起泡器中以提供气态钨源; 将可变温度起泡器设定到预定温度; 使载气通过可变温度起泡器并将载气的气态钨源运送到CVD真空室中; 将含氮反应气体引入CVD真空室中; 在沉积过程中使气态钨源和硅晶片表面上方的含氮反应物气体反应，以沉积W 1 / N 2 N 2 O 3 硅晶片; 并完成包含W＆lt; N＆gt; N＆gt; Y＆lt;＆lt;＆lt;＆lt;薄膜的集成电路。

公开(公告)号：US07157287B2

公开(公告)日：2007-01-02

申请号：US10855088

申请日：2004-05-27

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/20

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1241 ,  C23C18/1283 ,  C30B23/02 ,  C30B29/24 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1608

摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

摘要翻译： 制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

公开(公告)号：US06849467B1

公开(公告)日：2005-02-01

申请号：US10621863

申请日：2003-07-16

申请人： Tingkai Li ,  Wei Pan ,  Robert A. Barrowcliff ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei Pan ,  Robert A. Barrowcliff ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L27/11502 ,  H01L21/28291 ,  H01L21/31604 ,  H01L27/11585 ,  H01L27/1159 ,  H01L28/57 ,  H01L29/6684

摘要： A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0

摘要翻译： 在FeRAM中形成H 2钝化层的方法包括制备硅衬底; 在大马士革结构上沉积一层TiOx薄膜，其中0

公开(公告)号：US08264081B2

公开(公告)日：2012-09-11

申请号：US11311546

申请日：2005-12-19

申请人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

摘要翻译： 通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。 多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。 在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。 整个多层膜的厚度可以是大约50埃。 当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。 本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

公开(公告)号：US07192866B2

公开(公告)日：2007-03-20

申请号：US10326712

申请日：2002-12-19

申请人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L2221/1078

摘要： An alternating source MOCVD process is provided for depositing tungsten nitride thin films for use as barrier layers for copper interconnects. Alternating the tungsten precursor produces fine crystal grain films, or possibly amorphous films. The nitrogen source may also be alternated to form WN/W alternating layer films, as tungsten is deposited during periods where the nitrogen source is removed.

摘要翻译： 提供了用于沉积用作铜互连的阻挡层的氮化钨薄膜的交替源MOCVD工艺。 交替钨前体产生细晶粒膜或可能的非晶膜。 氮源也可以交替形成WN / W交替层膜，因为在氮源被去除的时期期间钨被沉积。

公开(公告)号：US07015138B2

公开(公告)日：2006-03-21

申请号：US09819296

申请日：2001-03-27

申请人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

公开(公告)号：US06939724B2

公开(公告)日：2005-09-06

申请号：US10640770

申请日：2003-08-13

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  David R. Evans ,  Sheng Teng Hsu ,  Wei Pan

IPC分类号： H01L27/04 ,  H01L21/20 ,  H01L21/822 ,  H01L45/00 ,  H01L21/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

公开(公告)号：US06777327B2

公开(公告)日：2004-08-17

申请号：US09820068

申请日：2001-03-28

申请人： Wei Pan ,  Jer-Shen Maa ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Jer-Shen Maa ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  C23C16/0209 ,  C23C16/18 ,  H01L21/28556 ,  H01L21/76864 ,  H01L21/76876

摘要： A rapid thermal process (RTP) provides steps wherein silicon wafers that are pre-coated with barrier metal films by either in-situ or ex-situ CVD or physical vapor deposition (PVD) are pre-treated, prior to deposition of a Cu film thereon, in a temperature range of between 250 and 550 degrees Celsius in a non-reactive gas such as hydrogen gas (H2), argon (Ar), or helium (He), or in an ambient vacuum. The chamber pressure typically is between 0.1 mTorr and 20 Torr, and the RTP time typically is between 30 to 100 seconds. Performing this rapid thermal process before deposition of the Cu film results in a thin, shiny, densely nucleated, and adhesive Cu film deposited on a variety of barrier metal surfaces. The pre-treatment process eliminates variations in the deposited Cu film caused by Cu precursors and is insensitive to variation in precursor composition, volatility, and other precursor variables. Accordingly, the process disclosed herein is an enabling technology for the use of metal organic CVD (MOCVD) Cu in IC fabrication.

摘要翻译： 快速热处理（RTP）提供了在沉积Cu膜之前预处理通过原位或原位CVD或物理气相沉积（PVD）预涂覆有阻挡金属膜的硅晶片的步骤 在非反应性气体如氢气（H 2），氩气（Ar）或氦气（He））或在环境真空中，在250-550摄氏度的温度范围内。 室压力通常在0.1mTorr和20Torr之间，并且RTP时间通常在30至100秒之间。 在沉积Cu膜之前进行这种快速热处理会导致沉积在各种阻挡金属表面上的薄而有光泽，致密成核和粘附的Cu膜。 预处理过程消除了由Cu前体引起的沉积的Cu膜的变化，并且对前体组成，挥发性和其它前体变量的变化不敏感。 因此，本文公开的方法是在IC制造中使用金属有机CVD（MOCVD）Cu的使能技术。

公开(公告)号：US06716744B2

公开(公告)日：2004-04-06

申请号：US10140460

申请日：2002-05-06

申请人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/28556 ,  H01L21/28562 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of adhering copper thin film to a substrate in an integrated circuit structure includes preparing a substrate, including forming active regions and trenches for interconnect structures; depositing a metal barrier layer on the substrate; depositing an ultra thin film layer of tungsten over the barrier metal layer; depositing a copper thin film on the tungsten ultra thin film layer; removing excess copper and tungsten to the level of the metal barrier layer; and completing the integrated circuit structure. An integrated circuit having a copper interconnect therein formed over a layer of barrier metal includes a substrate, including active regions, vias and trenches for interconnect structures; a metal barrier layer formed on the substrate, wherein said metal barrier layer is taken from the group of materials consisting of Ta, TiN, TaN, TaSiN and TiSiN, and formed to a thickness of between about 5 nm to 10 nm; an ultra thin film layer of tungsten formed on the barrier metal layer, said tungsten ultra thin film layer having a thickness of between about 1 nm to 5 nm; and a copper thin film layer formed on the tungsten ultra thin film layer to a thickness sufficient to fill the vias and trenches.

摘要翻译： 在集成电路结构中将铜薄膜粘合到基板上的方法包括制备基板，包括形成用于互连结构的有源区和沟槽; 在衬底上沉积金属阻挡层; 在所述阻挡金属层上沉积钨的超薄膜层; 在钨超薄膜层上沉积铜薄膜; 将过量的铜和钨去除到金属阻挡层的水平; 并完成集成电路结构。 在其上形成有铜互连的集成电路包括一个衬底，包括有源区，用于互连结构的通孔和沟槽; 形成在所述基板上的金属阻挡层，其中所述金属阻挡层取自由Ta，TiN，TaN，TaSiN和TiSiN组成的材料组，并形成为约5nm至10nm的厚度; 形成在所述阻挡金属层上的钨的超薄膜层，所述钨超薄膜层的厚度为约1nm至5nm; 以及形成在钨超薄膜层上的厚度足以填充通路和沟槽的厚度的铜薄膜层。