摘要:
Provided are a method of forming an insulating layer and a method of manufacturing a transistor using the method. The method of forming the insulating layer includes forming a preliminary insulating layer including silicon oxide (SiO2) on a silicon (Si)-containing substrate. A reactive gas containing ammonia (NH3) gas is supplied to the preliminary insulating layer. Nitrogen radicals (N*) and hydrogen radicals (H*) are generated from the ammonia gas using plasma. The hydrogen radicals combine with oxygen of the preliminary insulating layer, and the nitrogen radicals combine with the silicon oxide so that an insulating layer including hydroxides (OH) and silicon oxynitride (SiON) can be formed.
摘要:
In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.
摘要:
A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
摘要:
Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.
摘要:
A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer
摘要:
A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.
摘要:
A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.
摘要:
A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.
摘要:
First and second preliminary epitaxial layers are grown from single-crystalline seeds in openings in an insulation layer until the first and second epitaxial layers are connected to each other. While the first and second preliminary epitaxial layers are being grown, a connection structure of a material having an amorphous state is formed on a portion of the insulation layer located between the first and second preliminary epitaxial layers. The material having an amorphous state is then changed into material having a single-crystalline state. Thus, portions of the first and second epitaxial layers are connected to each other through the connection structure so that the epitaxial layers and the connection structure constitute a single-crystalline structure layer that is free of voids for use as a channel layer or the like of a semiconductor device.
摘要:
A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern, a silicon nitride layer pattern and a first polysilicon layer pattern that are sequentially stacked. The second gate pattern includes a second oxide layer pattern and a second polysilicon layer pattern. Related methods are also provided.