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公开(公告)号：US07132821B2
公开(公告)日：2006-11-07
申请号：US11103314
申请日：2005-04-11
CPC分类号： G05F1/565
摘要： Systems are provided for generating and distributing a plurality of reference currents on an integrated circuit. More particularly, an integrated circuit is provided which includes a reference current generating system. The reference current generating system includes a first reference current generator disposed at a first location of the integrated circuit which is operable to generate a plurality of first reference currents. A plurality of second reference current generators are disposed at a plurality of second locations of the integrated circuit. Each of the second reference current generators are operable to generate a second reference current from one of the plurality of first reference currents. In a particular example, the first location at which the first reference current generator is disposed is a central location and the second locations are disposed remote from the first location.
摘要翻译： 提供了用于在集成电路上生成和分配多个参考电流的系统。 更具体地，提供了包括参考电流产生系统的集成电路。 参考电流产生系统包括设置在集成电路的第一位置处的第一参考电流发生器，其可操作以产生多个第一参考电流。 多个第二参考电流发生器设置在集成电路的多个第二位置处。 每个第二参考电流发生器可操作以从多个第一参考电流之一产生第二参考电流。 在特定示例中，设置第一参考电流发生器的第一位置是中心位置，并且第二位置远离第一位置设置。
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52.发明授权Method and apparatus for controlling common-mode output voltage in fully differential amplifiers 有权用于控制全差分放大器中共模输出电压的方法和装置公开(公告)号：US07053712B2
公开(公告)日：2006-05-30
申请号：US10710745
申请日：2004-07-30
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/4565 , H03F3/45659 , H03F2200/78 , H03F2203/45418 , H03F2203/45424 , H03F2203/45521
摘要： A method for controlling the common-mode output voltage in a fully differential amplifier includes comparing a sensed common-mode output voltage of the fully differential amplifier to a reference voltage, and generating an error signal representing the difference between the sensed common-mode output voltage and the reference voltage. The error signal is utilized to control the body voltage of one or more FET devices included within the fully differential amplifier until the sensed common-mode output voltage is in agreement with said reference voltage.
摘要翻译： 一种用于控制全差分放大器中的共模输出电压的方法包括将全差分放大器的感测共模输出电压与参考电压进行比较，并产生一个误差信号，该误差信号表示检测到的共模输出电压 和参考电压。 误差信号用于控制包括在全差分放大器内的一个或多个FET器件的体电压，直到检测到的共模输出电压与所述参考电压一致。
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公开(公告)号：US06949981B2
公开(公告)日：2005-09-27
申请号：US10708233
申请日：2004-02-18
申请人： Joseph Natonio , Michael A. Sorna
发明人： Joseph Natonio , Michael A. Sorna
摘要： A voltage controlled oscillator (VCO) is provided which includes a threshold level setting circuit operable to set a lower variable threshold level and to set an upper variable threshold level. The VCO includes a frequency band selection unit operable to adjust a frequency band setting of the VCO to one of a plurality of frequency band settings. The VCO further includes a comparator operable to determine whether a control voltage of the VCO falls between the lower threshold level and the upper threshold level. The VCO further includes a threshold adjustment and calibration circuit operable to maintain the frequency band setting when the control voltage falls between the lower and upper threshold levels. Otherwise, when the control voltage lies below the lower threshold level, the lower threshold level is adjusted downward and the upper threshold level is adjusted upward, and when the control voltage lies above the upper threshold level, the frequency band selection is increased to a next higher frequency band.
摘要翻译： 提供了一种压控振荡器（VCO），其包括阈值电平设置电路，其可操作以设置较低的可变阈值电平并设置较高的可变阈值电平。 VCO包括频带选择单元，其可操作以将VCO的频带设置调整为多个频带设置中的一个。 VCO还包括比较器，其可操作以确定VCO的控制电压是否落在下阈值电平和上阈值电平之间。 VCO还包括阈值调整和校准电路，其可操作以在控制电压落在下限和上限阈值水平之间时维持频带设置。 否则，当控制电压低于下阈值电平时，下阈值电平向下调整，上阈值电平向上调整，当控制电压高于上阈值电平时，频段选择增加到下一阈值 较高频段。
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公开(公告)号：US5912928A
公开(公告)日：1999-06-15
申请号：US884117
申请日：1997-06-27
CPC分类号： H04L7/0008 , H04L25/4904
摘要： A clock encoding circuit, e.g., for Manchester encoding, for high speed data transmission (IEEE 1394) and a circuit for controlling data and encoded clock transmission. The clock encoding circuit includes two parallel to serial shift registers, a DATA register and a STROBE register, receiving data in parallel and shifted out at 100 MHz, 200 MHz or 400 MHz. The STROBE register receives every other bit of the data inverted. When both registers are clocked at the data transmission rate, data is shifted out of DATA register and the transmission clock is encoded in STROBE, shifted out of the STROBE register. Bit inversion may be with invertors receiving data as it is passed to the DATA register, or alternatively, after it is loaded into the DATA register. The circuit for controlling DATA and STROBE transmission includes the clock encoding circuit, a frequency matching register array and a loopback shift register. A control word is loaded into the loopback register and loops through the loopback register at the transmission rate, triggering data transfers from the frequency matching register array to the DATA and STROBE registers. All or part of the DATA and STROBE register contents is transmitted depending on the transmission rate.
摘要翻译： 时钟编码电路，例如用于曼彻斯特编码，用于高速数据传输（IEEE 1394）和用于控制数据和编码时钟传输的电路。 时钟编码电路包括两个并行到串行移位寄存器，一个DATA寄存器和一个STROBE寄存器，并行接收数据，并以100 MHz，200 MHz或400 MHz进行移出。 STROBE寄存器接收数据的每隔一位反转。 当两个寄存器以数据传输速率计时时，数据从DATA寄存器中移出，传输时钟以STROBE编码，移出STROBE寄存器。 位反转可以是反向器在数据被传递到DATA寄存器时接收数据，或者在其被加载到DATA寄存器之后。 用于控制DATA和STROBE传输的电路包括时钟编码电路，频率匹配寄存器阵列和环回移位寄存器。 控制字被加载到环回寄存器中，以传输速率循环回环寄存器，触发从频率匹配寄存器阵列到DATA和STROBE寄存器的数据传输。 根据传输速率传输全部或部分DATA和STROBE寄存器内容。
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公开(公告)号：US5132613A
公开(公告)日：1992-07-21
申请号：US620973
申请日：1990-11-30
CPC分类号： G01R31/2884
摘要： An integrated circuit test structure is comprised of a stacked substrate MLC space transformer (5). A top surface of an interface substrate (12) is employed for decoupling capacitor (36) placement. The top surface has metal conductors (20) exposed thereon for terminating power supply buses from a tester (1). Individual layers of a personalization substrate (14) are fabricated to redundantly extend internal power plane metalization (22) to the sidewalls. Redundant pads (26) are placed on each personalization layer to increase the surface area for side mount contact. Metal pads (18) are deposited over the exposed sidewall metal for forming a sidewall contact to the power planes within the personalization substrate. The personalization substrate is joined to the upper surface of the interface substrate and the sidewall contacts are conductively coupled by conductive members (40) to the interface substrate metal conductors (20), thereby providing a low inductance, low resistance DC path from the tester to a device under test (4). The decoupling capacitors are electrically coupled to the metal lines in close proximity the personalization substrate thereby minimizing the associated lead inductance and maximizing the effectiveness of the decoupling capacitors.
摘要翻译： 集成电路测试结构由层叠衬底MLC空间变压器（5）组成。 接口衬底（12）的顶表面用于去耦电容器（36）放置。 顶面具有暴露在其上的金属导体（20），用于从测试器（1）端接电源总线。 制造个性化衬底（14）的各个层以将内部功率平面金属化（22）冗余地扩展到侧壁。 冗余垫（26）放置在每个个性化层上以增加用于侧装接触的表面积。 金属焊盘（18）沉积在暴露的侧壁金属上，以形成与个性化衬底内的电源平面的侧壁接触。 个性化衬底连接到界面衬底的上表面，并且侧壁触点通过导电构件（40）导电耦合到界面衬底金属导体（20），从而提供从测试仪到低电阻的低电阻，低电阻DC路径 被测设备（4）。 去耦电容器紧邻个性化衬底电耦合到金属线，从而最小化相关的引线电感并最大限度地提高去耦电容器的有效性。
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公开(公告)号：US20120260016A1
公开(公告)日：2012-10-11
申请号：US13080799
申请日：2011-04-06
IPC分类号： G06F13/14
CPC分类号： G06F13/385 , G06F1/10 , G06F13/4072 , G11C7/1006 , G11C7/1066 , G11C7/1093
摘要： A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.
摘要翻译： 一种多用途物理（PHY）架构，其包括包括一个或多个位线并且通信地耦合到第一处理器的PHY连接。 PHY连接可配置为在第一处理器和第二处理器之间或第一处理器和存储器之间传送信号。 一个或多个位线被配置为当PHY连接被配置为在第一处理器和存储器之间传送信号时以双向方式携带信号处于第一电压。 当PHY连接被配置为在第一处理器和第二处理器之间传送信号时，一个或多个位线被配置为以第二电压单向地传送信号。 第二电压不同于第一电压。
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57.发明授权Automatic adaptive equalization method for high-speed serial transmission link 失效自动自适应均衡方法用于高速串行传输链路公开(公告)号：US07733964B2
公开(公告)日：2010-06-08
申请号：US11974967
申请日：2007-10-17
CPC分类号： H04L25/03057 , H04L25/03343
摘要： In a method for performing equalization of a communication system, a predetermined signal can be transmitted from a transmitter unit to a receiver unit in a downchannel direction on a transmission line, for example as a pair of differential signals which simultaneously transition in opposite directions on respective signal conductors of the transmission line. At the receiver unit, an eye opening of the signal received from the transmission line can be analyzed to determine equalization information. Equalization information can be transmitted from the receiver unit to the transmitter unit in an upchannel direction on the transmission line and be received at the transmitter unit. Using received equalization information, a transmission characteristic of the transmitter unit can be adjusted.
摘要翻译： 在用于执行通信系统的均衡的方法中，可以将预定信号从发射机单元发送到传输线上的下行信道方向上的接收机单元，例如作为在相应方向上同时沿相反方向转变的一对差分信号 传输线的信号导体。 在接收机单元，可以分析从传输线接收的信号的眼图，以确定均衡信息。 均衡信息可以在传输线上的上行方向上从接收机单元发送到发射机单元，并在发射机单元处接收。 使用接收到的均衡信息，可以调整发送单元的发送特性。
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公开(公告)号：US07719302B2
公开(公告)日：2010-05-18
申请号：US12215732
申请日：2008-06-30
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A method is provided for monitoring interconnect resistance within a semiconductor chip assembly, A semiconductor chip assembly can include a semiconductor chip having contacts exposed at a surface of the semiconductor chip and a substrate having exposed terminals in conductive communication with the contacts. A plurality of monitored elements of the semiconductor chip can include conductive interconnects, each interconnecting a respective pair of nodes of the semiconductor chip through wiring within the semiconductor chip. In an example of such method, a voltage drop across each monitored element is compared with a reference voltage drop across a respective reference element on the semiconductor chip at a plurality of different times during a lifetime of the semiconductor chip assembly. In that way, it can be detected when a resistance of such monitored element is over threshold. Based on a result of such comparison, a decision can be made whether to indicate an action condition.
摘要翻译： 提供了一种用于监测半导体芯片组件内的互连电阻的方法。半导体芯片组件可以包括具有在半导体芯片的表面处露出的触点的半导体芯片和具有与触点导电连通的露出端子的基板。 半导体芯片的多个受监测元件可以包括导电互连，每个导体互连通过半导体芯片内的布线互连半导体芯片的相应的一对节点。 在这种方法的示例中，在半导体芯片组件的寿命期间，跨越每个被监测元件的电压降与在半导体芯片上的相应参考元件上的参考电压降在多个不同时间进行比较。 以这种方式，当这种被监视的元件的电阻超过阈值时，可以检测它。 基于这种比较的结果，可以做出是否指示动作条件的决定。
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公开(公告)号：US07519130B2
公开(公告)日：2009-04-14
申请号：US10905705
申请日：2005-01-18
申请人： Louis L. Hsu , Matt R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Karl D. Selander , Michael A. Sorna , Huihao Xu
发明人： Louis L. Hsu , Matt R. Cordrey-Gale , James S. Mason , Philip J. Murfet , Karl D. Selander , Michael A. Sorna , Huihao Xu
IPC分类号： H04L25/34
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.
摘要翻译： 提供一种数据接收器，其包括具有交流（AC）发送接收模式和直流（DC）发送接收模式的前端接口电路。 前端接口电路包括偏移补偿电路，其可操作以补偿输入到数据接收器的一对差分信号之间的直流电压偏移。 前端接口电路还包括可操作以在（a）直流发送接收模式和（b）交流发送接收模式之间切换的AC / DC选择单元，使得数据接收器可操作于（i）直流传输 偏移补偿电路被禁用的模式，（ii）使能偏移补偿电路的直流传输模式，（iii）偏移补偿电路被禁用的AC传输模式，以及（iv）AC传输接收 偏移补偿电路使能的模式。
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公开(公告)号：US07394283B2
公开(公告)日：2008-07-01
申请号：US11467349
申请日：2006-08-25
IPC分类号： H03K17/16
CPC分类号： H03K19/018528
摘要： A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.
摘要翻译： 提供信号再生器，其包括共模参考发生器和信号转换器电路。 产生共模参考电压电平，其相对于用于制造共模参考发生器的工艺中的至少一个，提供给共模参考发生器的电源电压的电平或共模参考电压的温度可变 模式参考发生器运行。 信号转换器电路接收包括第一输入信号和第二输入信号的差分发送信号对，并输出表示由差分发送信号对承载的信息的单端输出信号。 使用来自共模参考发生器的反馈信号，反馈控制块根据共模参考电压电平控制单端输出信号的共模电平。
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