公开(公告)号：US08643987B2

公开(公告)日：2014-02-04

申请号：US13464131

申请日：2012-05-04

申请人： Albert M. Chu ,  Joseph A. Iadanza ,  Mujahid Muhammad ,  Daryl M. Seitzer ,  Rohit Shetty ,  Jane S. Tu

发明人： Albert M. Chu ,  Joseph A. Iadanza ,  Mujahid Muhammad ,  Daryl M. Seitzer ,  Rohit Shetty ,  Jane S. Tu

IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H9/04 ,  H02H3/22

CPC分类号： H02H9/046

摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.

摘要翻译： 本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。 在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲 选择负偏压电源，在正常工作期间关闭ESD钳位。

公开(公告)号：US20130293991A1

公开(公告)日：2013-11-07

申请号：US13464131

申请日：2012-05-04

申请人： Albert M. Chu ,  Joseph A. Iadanza ,  Mujahid Muhammad ,  Daryl M. Seitzer ,  Rohit Shetty ,  Jane S. Tu

发明人： Albert M. Chu ,  Joseph A. Iadanza ,  Mujahid Muhammad ,  Daryl M. Seitzer ,  Rohit Shetty ,  Jane S. Tu

IPC分类号： H02H9/04 ,  H01L27/06

CPC分类号： H02H9/046

摘要： Aspects of the invention provide an electrostatic discharge (ESD) protection device for eliminating current leakage, and a related method. In one embodiment, an ESD protection device includes: a resistor-capacitor (RC) circuit for receiving a power supply voltage; an ESD clamp including a plurality of n-type field-effect transistors (nFETs) for protecting the IC during an ESD event; a trigger circuit for receiving an output of the RC circuit and generating a trigger pulse to turn on the ESD clamp during the ESD event; and an nFET bias selection circuit connected to the trigger circuit, the nFET bias selection circuit for selecting one of: a low voltage supply or a negative bias voltage supply for the trigger circuit, such that the trigger circuit generates a trigger pulse, in response to selecting the negative bias voltage supply, to turn off the ESD clamp during normal operation.

摘要翻译： 本发明提供一种用于消除电流泄漏的静电放电（ESD）保护装置及相关方法。 在一个实施例中，ESD保护装置包括：用于接收电源电压的电阻器 - 电容器（RC）电路; 包括用于在ESD事件期间保护IC的多个n型场效应晶体管（nFET）的ESD钳位; 触发电路，用于接收RC电路的输出并产生触发脉冲以在ESD事件期间导通ESD钳位; 以及连接到触发电路的nFET偏置选择电路，nFET偏置选择电路，用于选择触发电路的低电压电源或负偏置电压源，使得触发电路响应于触发电路产生触发脉冲 选择负偏压电源，在正常工作期间关闭ESD钳位。

公开(公告)号：US07814449B2

公开(公告)日：2010-10-12

申请号：US11873515

申请日：2007-10-17

申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Joseph A. Iadanza

发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Joseph A. Iadanza

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： Disclosed are embodiments of a design structure for a variable-delay field effect transistor (FET) having multiple source regions that can be individually and selectively biased to provide an electrical connection to a single drain region. Delay is a function of which of the multiple source regions is/are selectively biased as well as a function of gate resistance and capacitance. Such a variable-delay FET can be incorporated into a phase adjusting circuit, which uses gate propagation delays to selectively phase adjust an input signal. The phase adjusting circuit can be tuned by incorporating non-salicided resistances and additional capacitance at various positions on the gate structure. The phase adjusting circuit can further be modified into a phase adjusting mixer circuit that enables a phase adjusted signal to be combined with an additional signal.

摘要翻译： 公开了具有多个源极区域的可变延迟场效应晶体管（FET）的设计结构的实施例，其可被单独地和选择性地偏置以提供到单个漏极区域的电连接。 延迟是多个源极区域中的哪一个被选择性偏置以及栅极电阻和电容的函数的函数。 这样的可变延迟FET可以并入相位调整电路中，该相位调整电路使用栅极传播延迟来选择性地相位调整输入信号。 相位调整电路可以通过在栅极结构上的各个位置并入非水银电阻和附加电容来调节。 相位调整电路可以进一步修改为使相位调整信号与附加信号组合的相位调整混频器电路。

公开(公告)号：US20100019816A1

公开(公告)日：2010-01-28

申请号：US12573910

申请日：2009-10-06

申请人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Joseph A. Iadanza

发明人： Wagdi W. Abadeer ,  Anthony R. Bonaccio ,  Joseph A. Iadanza

IPC分类号： H03K5/13

CPC分类号： H03K5/06 ,  H03K2005/00052 ,  H03K2005/00058

摘要： Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.

摘要翻译： 这里公开了可编程相位调整电路，可编程相位调整混频器电路和这些电路的设计结构的实施例。 这些电路包括连接在输入和输出节点之间的可变延迟器件。 该器件包括多个FET，其输入扩散区通过开关连接到电压轨，使得它们可以被选择性偏置，与输入节点串联连接的栅极，使得周期性输入信号可以顺序地传播通过 门和输出扩散区域并联连接到输出节点。 当可变延迟装置关闭时，电流源连接在输出节点和另一个电压轨道之间，用于偏置输出节点。 可变延迟装置使得能够作为传播延迟的函数对周期性输入信号进行可选相位调整的小增量的电路。

公开(公告)号：US20090152543A1

公开(公告)日：2009-06-18

申请号：US11957584

申请日：2007-12-17

申请人： Anthony R. Bonaccio ,  Joseph A. Iadanza

发明人： Anthony R. Bonaccio ,  Joseph A. Iadanza

IPC分类号： G01R31/02 ,  H01L21/66 ,  H01L23/58

CPC分类号： H01L22/14 ,  G06F17/5045 ,  G06F2217/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system, structure and method is provided for providing dynamic optimization of integrated circuits using a non-contact method of selection, and a design structure on which a subject circuit resides. The method is provided for optimizing an electronic system having at least one integrated circuit. The method includes storing a target performance voltage of the at least one integrated circuit; remotely querying the at least one integrated circuit to obtain the target performance voltage; and providing an operational voltage of a next-level assembly according to the stored target performance voltage.

摘要翻译： 提供了一种用于使用非接触式选择方法提供集成电路的动态优化的系统，结构和方法以及被摄体电路所在的设计结构。 该方法用于优化具有至少一个集成电路的电子系统。 该方法包括存储至少一个集成电路的目标性能电压; 远程查询所述至少一个集成电路以获得所述目标性能电压; 以及根据存储的目标性能电压提供下一级组件的工作电压。

公开(公告)号：US20080304192A1

公开(公告)日：2008-12-11

申请号：US11760856

申请日：2007-06-11

申请人： Bradford L. Hunter ,  Joseph A. Iadanza

发明人： Bradford L. Hunter ,  Joseph A. Iadanza

IPC分类号： H02H3/00 ,  H02H3/24

CPC分类号： H02H11/006 ,  Y10S323/901 ,  Y10T307/729 ,  Y10T307/832 ,  Y10T307/858

摘要： A method and structure for preventing operation of a circuit in a high current operating region by disabling a start-up circuit until a power supply headroom is detected at a predetermined voltage level.

摘要翻译： 一种用于通过禁用启动电路直到在预定电压电平检测到电源余量来防止电路在高电流操作区域中的操作的方法和结构。

公开(公告)号：US06960837B2

公开(公告)日：2005-11-01

申请号：US09683872

申请日：2002-02-26

申请人： Joseph A. Iadanza

发明人： Joseph A. Iadanza

IPC分类号： H01L23/48 ,  H01L23/485 ,  H01L23/52 ,  H01L29/40 ,  H01L31/00

CPC分类号： H01L24/73 ,  H01L23/481 ,  H01L24/02 ,  H01L24/10 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit, comprising: a predefined block of functional circuitry having a plurality of I/O pins; and a backside I/O pad electrically connected to each I/O pin through a backside via of the integrated circuit.

摘要翻译： 一种集成电路，包括：具有多个I / O引脚的功能电路的预定义块; 以及通过集成电路的背面通孔电连接到每个I / O引脚的背面I / O焊盘。

公开(公告)号：US08841893B2

公开(公告)日：2014-09-23

申请号：US13213578

申请日：2011-08-19

申请人： John F. Bulzacchelli ,  Carrie E. Cox ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

发明人： John F. Bulzacchelli ,  Carrie E. Cox ,  Zeynep Toprak-Deniz ,  Daniel J. Friedman ,  Joseph A. Iadanza ,  Todd M. Rasmus

IPC分类号： G05F1/575

CPC分类号： G05F1/575

摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.

摘要翻译： 双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢 比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

公开(公告)号：US08711022B2

公开(公告)日：2014-04-29

申请号：US13526915

申请日：2012-06-19

申请人： Joseph A. Iadanza

发明人： Joseph A. Iadanza

IPC分类号： H03M1/78

CPC分类号： H03M1/785

摘要： A resistor-2 resistor (R-2R) digital-to-analog converter with resistor network reversal and methods of use are disclosed. A circuit includes a plurality of resistor stacks and a plurality of separation resistors which separate the resistor stacks. The circuit further includes a plurality of selection devices connected to a respective one of the plurality of resistor stacks. The circuit also includes a first termination resistor stack connected to a drain of a first resistor stack of the plurality of resistor stacks and a second termination resistor stack connected to a drain of a last resistor stack of the plurality of resistor stacks. The circuit further includes a first switch connected to the drain of the first resistor stack of the plurality of resistor stacks and an output. The circuit also includes a second switch connected to the drain of the last resistor stack of the plurality of resistor stacks and the output.

摘要翻译： 公开了一种具有电阻网络反转的电阻器2电阻（R-2R）数模转换器及其使用方法。 电路包括多个电阻器堆叠和分离电阻器堆叠的多个分离电阻器。 电路还包括连接到多个电阻器堆叠中的相应一个的多个选择装置。 电路还包括连接到多个电阻器堆叠中的第一电阻器堆叠的漏极的第一终端电阻器堆叠和连接到多个电阻器堆叠的最后一个电阻器堆叠的漏极的第二终端电阻器堆叠。 电路还包括连接到多个电阻器堆叠中的第一电阻器堆叠的漏极的第一开关和输出端。 电路还包括连接到多个电阻器堆叠的最后一个电阻器堆叠的漏极和输出端的第二开关。

公开(公告)号：US07868809B2

公开(公告)日：2011-01-11

申请号：US12389618

申请日：2009-02-20

申请人： Joseph A. Iadanza ,  Benjamin T Voegeli

发明人： Joseph A. Iadanza ,  Benjamin T Voegeli

IPC分类号： H03M1/78

CPC分类号： H03M1/06 ,  H03M1/682 ,  H03M1/765

摘要： A resistor-based digital to analog converter (DAC) having mux fastpaths, which selectively connect a subset (or an entirety) of voltage divider nodes in a DAC to either a higher level of multiplexor hierarchy, or a DAC output node, effectively bypassing one or more levels of multiplexor devices. In addition, the fastpaths may selectively connect lower levels of multiplexor hierarchy to higher levels of multiplexor hierarchy and/or a DAC output node.

摘要翻译： 具有多路复用快速路径的基于电阻的数模转换器（DAC），其将DAC中的分压器节点的子集（或整体）有选择地连接到更高级别的多路复用器层级或DAC输出节点，有效地绕过一个 或更多级别的多路复用器设备。 此外，快速路径可以选择性地将较低级别的多路复用器层级连接到更高级别的多路复用器层级和/或DAC输出节点。