公开(公告)号：US07142454B2

公开(公告)日：2006-11-28

申请号：US10243315

申请日：2002-09-12

申请人： Tien-Chun Yang ,  Ming-Huei Shieh ,  Kurihara Kazuhiro ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Ming-Huei Shieh ,  Kurihara Kazuhiro ,  Pau-Ling Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0458 ,  G11C16/0475 ,  G11C16/0491

摘要： A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.

摘要翻译： 公开了一种用于非易失性存储单元阵列中的列选择的系统和方法。 一组存储单元被布置成具有行（X维）和列（Y维）的矩形阵列。 在一行中，存储器单元的源极和漏极被连接以形成线性链。 公共字线连接到行中的每个门。 单独的列线耦合到链的相邻存储器单元之间的每个节点。 四列Y解码器用于选择用于感测操作的列线。 在感测操作期间，将电压源施加到四列中的两条线。 可以感测一列列线上的电流以提供用于读取或验证的测量。

公开(公告)号：US06859393B1

公开(公告)日：2005-02-22

申请号：US10264387

申请日：2002-10-04

申请人： Tien-Chun Yang ,  Shigekazu Yamada ,  Ming-Huei Shieh ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Shigekazu Yamada ,  Ming-Huei Shieh ,  Pau-Ling Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  G11C2216/14

摘要： A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.

摘要翻译： 用于闪存的页面读取和页面写入的接地结构。 闪存单元的阵列结构包括多个扇区。 每个扇区包括I / O块加参考阵列和冗余单元阵列。 每个I / O块包括子I / O块。 I / O块内的每个子I / O块以及包括参考单元，冗余单元和边缘结构的其他结构都耦合到独特的接地参考信号。 这些独特的接地参考信号可以选择性地耦合到系统接地或偏置的接地参考。 这种新颖的接地布置使得能够同时读取来自每个子I / O块的一个位的页面读取操作。 另外，每个I / O块的一位可以同时编程。 此外，可以选择性地调整阵列的单元的接地参考电压以优化操作。

公开(公告)号：US06813735B1

公开(公告)日：2004-11-02

申请号：US09676623

申请日：2000-10-02

申请人： Kazuhiro Kurihara ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Pau-Ling Chen

IPC分类号： G11C2900

CPC分类号： G11C29/76 ,  G11C16/0491 ,  G11C29/846

摘要： The present invention discloses methods and systems of accomplishing I/O-based redundancy for a memory device that includes two-bit memory cells. The memory device includes a core two-bit memory cell array and a redundant two-bit memory cell array. The configuration of the core two-bit memory cell array is non-uniform such that the two-bit memory cells therein are not arranged in a sequential order. Due to the non-uniform configuration, I/O based redundancy is accomplished by decoding the addresses with a redundant Y-decoder circuit and translating the addresses using an address translation circuit. The translated addresses identify the location of the two-bit memory cells within the non-uniform core two-bit memory cell array. The decoding of the addresses configures the redundant two-bit memory cell array to provide a configuration that matches the two-bit memory cells in the location identified by the translated address.

摘要翻译： 本发明公开了一种为包含2位存储单元的存储器件完成基于I / O的冗余的方法和系统。 存储器件包括核心的两位存储单元阵列和冗余的两位存储单元阵列。 核心2位存储单元阵列的配置是不均匀的，使得其中的2位存储单元不按顺序排列。 由于不均匀配置，基于I / O的冗余是通过使用冗余Y解码器电路解码地址并使用地址转换电路翻译地址来实现的。 翻译的地址标识不均匀核心2位存储单元阵列内的两位存储单元的位置。 地址的解码配置冗余的两比特存储单元阵列以提供与由翻译的地址标识的位置中的两比特存储器单元匹配的配置。

公开(公告)号：US06744666B1

公开(公告)日：2004-06-01

申请号：US10243792

申请日：2002-09-12

申请人： Santosh Yachareni ,  Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Pau-Ling Chen

发明人： Santosh Yachareni ,  Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Pau-Ling Chen

IPC分类号： G11C1134

CPC分类号： G11C16/10 ,  G11C2216/14 ,  G11C2216/16

摘要： Embodiments of the present invention are directed to a method and system to minimize page programming time for page programmable memory devices. In one embodiment, the present invention comprises program logic that programs a page programmable memory device with a plurality of words during a page programming cycle and a detector coupled to the program logic that identifies a particular word in that plurality of words which does not require programming. When the detector identifies a particular word which does not require programming, it sends an indication to the program logic component which, in response to the signal, reduces the length of the page programming cycle.

摘要翻译： 本发明的实施例涉及一种使页面可编程存储器件的页面编程时间最小化的方法和系统。 在一个实施例中，本发明包括在页面编程周期期间用多个单词编程页面可编程存储器件的程序逻辑和耦合到程序逻辑的检测器，该程序逻辑识别出不需要编程的多个单词中的特定单词 。 当检测器识别不需要编程的特定字时，它向程序逻辑组件发送指示，该程序逻辑组件响应于该信号减少了页面编程周期的长度。

公开(公告)号：US06728160B1

公开(公告)日：2004-04-27

申请号：US10243433

申请日：2002-09-12

申请人： Tien-Chun Yang ,  Kurihara Kazuhiro ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Kurihara Kazuhiro ,  Pau-Ling Chen

IPC分类号： G11C800

CPC分类号： G11C16/24 ,  G11C7/1051 ,  G11C7/12

摘要： A path gate driver circuit of the present invention includes a shunt stage, a level shifter stage, a pull-up stage, and an output stage. The shunt stage has a control terminal coupled to a supply, and an input terminal coupled to a control signal path. The level shifter stage has a first control terminal coupled to the control signal path, a second control terminal coupled to an output terminal of the shunt stage, a first input terminal coupled to a boost-low supply, and a second input terminal coupled to a boost-high supply. The pull-up stage has a control terminal coupled to an output terminal of the level shifter stage, and an input terminal coupled to the boost-high supply. The output stage has a first control terminal coupled to the output terminal of the shunt stage and an output terminal of the pull-up stage, a second control terminal coupled to the control signal path a first input terminal coupled to the boost-low supply, and a second input terminal coupled to the boost-high supply. A boosted control signal is provided at the output terminal of the output stage in response to the control.

摘要翻译： 本发明的路径栅极驱动电路包括分路级，电平转换级，上拉级和输出级。 分流级具有耦合到电源的控制端子和耦合到控制信号路径的输入端子。 电平移位器级具有耦合到控制信号路径的第一控制端，耦合到并联级的输出端的第二控制端，耦合到升压低电源的第一输入端和耦合到 增加高的供应。 上拉级具有耦合到电平移位器级的输出端子的控制端子和耦合到升压高电源的输入端子。 输出级具有耦合到并联级的输出端和上拉级的输出端的第一控制端，耦合到控制信号路径的第二控制端，耦合到升压低电源的第一输入端， 以及耦合到所述升压高电源的第二输入端子。 响应于该控制，在输出级的输出端提供升压控制信号。

公开(公告)号：US06424570B1

公开(公告)日：2002-07-23

申请号：US09892189

申请日：2001-06-26

申请人： Binh Q. Le ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： H02M3/073

摘要： A system is described for generating a charge pump voltage for flash memory operations, wherein a supply voltage detection circuit (e.g., analog to digital converter, digital thermometer) is configured to detect a supply voltage value and generate one or more supply voltage level detection signals associated therewith. The system further includes a charge pump circuit comprising one or more stages operable to receive a supply voltage and generate the charge pump output voltage having a value greater than the supply voltage, and a charge pump compensation circuit operably coupled to the supply voltage detection circuit and the charge pump circuit. The charge pump compensation circuit is operable to receive the one or more output signals from the supply voltage detection circuit and modulate a capacitive loading associated with the charge pump circuit based on the one or more output signals, thereby creating an improved low power charge pump which uses a modulated pumping capacitance to compensate for fluctuations of the input power supply (for example, VCC), to produce a slow ripple and low noise output which may be used as a pumped voltage for various mode operations (e.g., erase, program modes) of memory cells.

摘要翻译： 描述了一种用于产生用于闪速存储器操作的电荷泵电压的系统，其中电源电压检测电路（例如，模数转换器，数字温度计）被配置为检测电源电压值并产生一个或多个电源电压电平检测信号 相关联。 该系统还包括电荷泵电路，其包括一个或多个级，可操作以接收电源电压并产生具有大于电源电压的值的电荷泵输出电压;以及电荷泵补偿电路，其可操作地耦合到电源电压检测电路和 电荷泵电路。 电荷泵补偿电路可操作以从电源电压检测电路接收一个或多个输出信号，并且基于该一个或多个输出信号调制与电荷泵电路相关联的电容性负载，从而产生改进的低功率电荷泵， 使用调制的泵浦电容来补偿输入电源的波动（例如VCC），以产生慢波纹和低噪声输出，其可用作用于各种模式操作（例如擦除，编程模式）的泵浦电压， 的记忆细胞。

公开(公告)号：US06292399B1

公开(公告)日：2001-09-18

申请号：US09609897

申请日：2000-07-03

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk

IPC分类号： G11C1606

CPC分类号： G11C16/28

摘要： Control circuitry and a method for generating an accurate drain voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Select gate transistors are provided which have their conduction path being coupled between a power supply voltage and a drain of one of the selected memory core cells. A differential amplifier circuit is responsive to a bitline voltage corresponding to a drain voltage of the selected memory core cells and a reference voltage for generating a select gate voltage. The select gate voltage is decreased when the bitline voltage is higher than a target voltage and is increased when the bitline voltage is lower than the target voltage. A source follower circuit is responsive to the select gate voltage for generating the bitline voltage which is maintained at the target voltage. The control gates of the select gate transistors are connected to receive the select gate voltage for maintaining the voltage at the drain of the selected memory core cells to be approximately constant.

摘要翻译： 提供控制电路和在读操作模式期间为半导体存储器件中的选定存储核心单元产生准确的漏极电压的方法。 提供选择栅极晶体管，其导通路径耦合在所选存储核心单元之一的电源电压和漏极之间。 差分放大器电路响应于对应于所选择的存储器单元的漏极电压的位线电压和用于产生选择栅极电压的参考电压。 当位线电压高于目标电压时，选择栅极电压降低，并且当位线电压低于目标电压时，选择栅极电压增加。 源极跟随器电路响应选择栅极电压以产生保持在目标电压的位线电压。 选择栅极晶体管的控制栅极被连接以接收选择栅极电压，以将所选择的存储器核心单元的漏极处的电压保持为大致恒定。

公开(公告)号：US06208561B1

公开(公告)日：2001-03-27

申请号：US09593303

申请日：2000-06-13

申请人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Kazuhiro Kurihara ,  Pau-Ling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/08

摘要： An apparatus and a method for reducing capacitive loading in a Flash memory X-decoder so as to accurately control the voltages as selected wordlines and block select lines are provided. A decoding structure separately applies a first boosted voltage to the wordline N-well region and a second boosted voltage to the selected wordline so as to reduce capacitive loading on the selected wordline due to heavy capacitive loading associated with the wordline N-well region. The decoding structure further applies a third boosted voltage to the select gate N-well region and a fourth boosted voltage to the block select line so as to reduce capacitive loading on the block select line due to heavy capacitive loading associated with the select gate N-well region. As a consequence, an accurate voltage can be created quickly at the selected wordline since its capacitive loading path is very small.

摘要翻译： 提供了一种用于降低闪存X解码器中的电容负载以便精确地将电压控制为选择的字线和块选择线的装置和方法。 解码结构分别将第一升压电压施加到字线N阱区域，并将第二升压电压施加到所选择的字线，以便由于与字线N阱区域相关联的重电容性负载而减小所选字线上的容性负载。 解码结构还将第三升压电压施加到选择栅极N阱区域，并将第四升压电压施加到块选择线，以便由于与选择栅极N相关联的重电容负载而减小块选择线上的电容负载， 井区。 因此，由于其电容加载路径非常小，所以可以在所选字线处快速创建精确的电压。

公开(公告)号：US06177322B1

公开(公告)日：2001-01-23

申请号：US09177817

申请日：1998-10-23

申请人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

发明人： Narbeh Derhacobian ,  Pau-Ling Chen ,  Hao Fang ,  Timothy Thurgate

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L29/1033 ,  H01L29/41775

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant, masking the source/drain regions from the conventional threshold adjust implant, providing a thick gate oxide layer, employing a very lightly doped n-type implant in lieu of conventional n+ and LDD implants, and forming contacts to the source and drain regions at a minimum distance from the gate.

摘要翻译： 形成表现出高选通二极管击穿电压的高压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩盖来自常规场注入的高电压接头来提供高门控二极管击穿电压，从常规阈值调整注入屏蔽源极/漏极区域，提供厚栅极氧化物层，采用非常轻掺杂的n型注入 代替常规的n +和LDD植入物，并且在与栅极最小距离处形成与源区和漏区的接触。

公开(公告)号：US5815438A

公开(公告)日：1998-09-29

申请号：US810170

申请日：1997-02-28

申请人： Sameer S. Haddad ,  Pau-Ling Chen

发明人： Sameer S. Haddad ,  Pau-Ling Chen

IPC分类号： G11C16/26 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C16/26

摘要： There is provided an improved method for eliminating hot-carrier disturb during a read operation in a NAND memory architecture in which a floating gate device is used as a select gate. A first positive pulse voltage having a ramp-rate characteristic on its leading edge is applied to the drain of the floating gate device during the read operation. Simultaneously, a second positive pulse voltage is applied to the control gate of the floating gate device during the read operation so as to overlap the first positive pulse voltage.

摘要翻译： 提供了一种在浮动栅极器件用作选择栅极的NAND存储器架构中在读取操作期间消除热载波干扰的改进方法。 在读取操作期间，在其前沿具有斜率特性的第一正脉冲电压被施加到浮动栅极器件的漏极。 同时，在读取操作期间，第二正脉冲电压施加到浮动栅极器件的控制栅极，以便与第一正脉冲电压重叠。