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    Network interface with double data rate and delay locked loop
    51.
    发明申请
    Network interface with double data rate and delay locked loop 有权
    具有双数据速率和延迟锁定环路的网络接口

    公开(公告)号：US20070033428A1

    公开(公告)日：2007-02-08

    申请号：US11580956

    申请日：2006-10-16

    申请人： Jonathan Lin ,  Yong Jiang

    发明人： Jonathan Lin ,  Yong Jiang

    IPC分类号： G06F1/00

    CPC分类号： G06F13/385 ,  H03L7/0812 ,  H04J3/0697 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/40

    摘要： A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e.g., from internal device logic) is output from the data I/O device to the at least one port. The external clock signal is input to the programmable delay locked loop, which outputs an output clock signal having a frequency equal to the frequency of the external clock signal, in synchronization with the data being output.

    摘要翻译： 提供一种网络设备，其包括设备输入，至少一个端口，倍频器，数据I / O设备和可编程延迟锁定环路。 倍频器耦合到输入并被配置为接收输入信号并输出​​具有输入信号频率的两倍的输出信号。 数据I / O设备被配置为基于参考时钟信号输出数据。 可编程延迟锁定环路耦合到设备输入端并被配置为接收输入信号并自动输出来自输入信号的异相预定量的输出信号。 在器件输入端接收的外部时钟信号输入倍频器。 倍频器的输出作为参考时钟输入到数据I / O设备。 数据（例如，从内部设备逻辑）从数据I / O设备输出到至少一个端口。 外部时钟信号被输入到可编程延迟锁定环路，与输出的数据同步地输出具有等于外部时钟信号频率的频率的输出时钟信号。

    Method and apparatus for glitch-free control of a delay-locked loop in a network device
    52.
    发明申请
    Method and apparatus for glitch-free control of a delay-locked loop in a network device 有权
    网络设备中延迟锁定环路无故障控制的方法和装置

    公开(公告)号：US20060290396A1

    公开(公告)日：2006-12-28

    申请号：US11511309

    申请日：2006-08-29

    申请人： Yong Jiang

    发明人： Yong Jiang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/089

    摘要： A method of controlling a delay-locked loop (DLL) module is disclosed. The method includes the steps of receiving a clock signal, comparing the received clock signal with a reference clock signal to determine whether a required phase difference between the signals is within specified tolerances, producing a correction signal when the required phase difference between the received clock and reference clock signals is not within the specified tolerances, utilizing the correction signal to change a delay setting and forwarding the correction signal to slave DLL modules in communication with the DLL module. The comparing, producing, utilizing and forwarding steps are performed only after a period of time has elapsed from a prior incidence of the comparing, producing, utilizing and forwarding steps, where the period of time is sufficient to allow the DLL to settle and no extraneous results are produced.

    摘要翻译： 公开了一种控制延迟锁定环（DLL）模块的方法。 该方法包括以下步骤：接收时钟信号，将接收到的时钟信号与参考时钟信号进行比较，以确定信号之间所需的相位差是否在规定的容限内，当所接收的时钟与所接收的时钟之间的所需相位差产生校正信号 参考时钟信号不在规定的公差范围内，利用校正信号改变延迟设置并将校正信号转发到与DLL模块通信的从属DLL模块。 比较，生成，利用和转发步骤仅在经过比较，产生，利用和转发步骤的先前发生的时间段之后才执行，其中该时间段足以允许DLL定居并且无外来 产生结果。

    Mist iron
    53.
    发明授权
    Mist iron 有权
    薄雾铁

    公开(公告)号：US07093384B2

    公开(公告)日：2006-08-22

    申请号：US10498770

    申请日：2002-12-03

    申请人： Nyik Siong Wong ,  Yong Jiang ,  Tao Guo ,  Kumar Asok SO Kasevan

    发明人： Nyik Siong Wong ,  Yong Jiang ,  Tao Guo ,  Kumar Asok SO Kasevan

    IPC分类号： D06F75/22

    CPC分类号： D06F75/22 ,  D06F75/10

    摘要： An iron comprising a housing (1), a heatable soleplate (4) and means for generating very fine liquid droplets to be expelled from at least one discharge opening (9) of the iron, said means comprising at least one air passage (8) for pressurized air supply and at least one liquid passage (13) for pressurized liquid supply, said air passage (8) and said liquid passage (13) communicating with each other for mixing air and liquid, said mixture of air and liquid being supplied to the discharge opening (9). To improve the generation of fine liquid droplets (mist) an outlet of the liquid passage (8) ends into the air passage (13) upstream of the discharge opening (9) to introduce liquid into the air passage and an outlet of the air passage is provided with a nozzle (10) having said discharge opening (9). Preferably the pressurized air and liquid supply is obtained by means of electric pumps (6,7). The liquid may be water or a (diluted) additive liquid.

    摘要翻译： 一种熨斗，包括壳体（1），可加热底板（4）和用于产生要从铁的至少一个排放开口（9）排出的非常细的液滴的装置，所述装置包括至少一个空气通道（8） 用于加压空气供应和用于加压液体供应的至少一个液体通道（13），所述空气通道（8）和所述液体通道（13）彼此连通以混合空气和液体，所述空气和液体混合物供应到 排出口（9）。 为了改善细液滴（雾）的产生，液体通道（8）的出口在排出口（9）的上游端部进入空气通道（13），以将液体引入空气通道和空气通道的出口 设置有具有所述排出口（9）的喷嘴（10）。 优选地，加压空气和液体供应通过电动泵（6,7）获得。 液体可以是水或（稀释的）添加剂液体。

    Network interface using programmable delay and frequency doubler
    54.
    发明申请
    Network interface using programmable delay and frequency doubler 有权
    网络接口采用可编程延迟和倍频器

    公开(公告)号：US20050268138A1

    公开(公告)日：2005-12-01

    申请号：US11180628

    申请日：2005-07-14

    申请人： Jonathan Lin ,  Yong Jiang

    发明人： Jonathan Lin ,  Yong Jiang

    IPC分类号： H03L7/00 ,  H04J3/06 ,  H04L7/00 ,  H04L7/033 ,  H04L25/14 ,  G06F1/12

    CPC分类号： H03L7/00 ,  H04J3/0697 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/0337 ,  H04L7/0338 ,  H04L25/14

    摘要： A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

    摘要翻译： 网络设备包括输入，至少一个端口，倍频器，数据I / O设备和可变延迟电路。 该输入用于接收外部时钟信号。 倍频器耦合到输入并被配置为接收输入信号并输出​​具有输入信号倍频的输出信号。 数据I / O设备被配置为基于参考时钟信号将数据输出到至少一个端口。 可变延迟电路位于数据I / O设备和至少一个端口之间。 在输入端接收的外部时钟信号输入倍频器。 倍频器的输出信号作为参考时钟信号施加到数据I / O装置，输出数据被可变延迟电路延迟。

    Water filter element
    56.
    外观设计
    Water filter element 有权

    公开(公告)号：USD1048303S1

    公开(公告)日：2024-10-22

    申请号：US29858019

    申请日：2022-10-27

    申请人： Yong Jiang

    设计人： Yong Jiang

    摘要： FIG. 1 is a front, right and top perspective view of a water filter element, showing my design.
    FIG. 2 is a rear, right and bottom perspective view thereof.
    FIG. 3 is a front elevation view thereof.
    FIG. 4 is a rear elevation view thereof.
    FIG. 5 is a left side elevation view thereof.
    FIG. 6 is a right side elevation view thereof.
    FIG. 7 is a top plan view thereof; and,
    FIG. 8 is a bottom plan view thereof.
    The broken lines depict portions of the water filter element that form no part of the claimed design.

    METHODS AND APPARATUS TO SUPPORT DYNAMIC ADJUSTMENT OF GRAPHICS PROCESSING UNIT FREQUENCY
    58.
    发明申请
    METHODS AND APPARATUS TO SUPPORT DYNAMIC ADJUSTMENT OF GRAPHICS PROCESSING UNIT FREQUENCY 审中-公开
    支持图形处理单元频率的动态调整的方法和装置

    公开(公告)号：US20170076422A1

    公开(公告)日：2017-03-16

    申请号：US15122108

    申请日：2014-03-27

    申请人： Lei Shen ,  Guei-Yuan Lueh ,  Yong Jiang ,  lntel Corporation

    发明人： Lei Shen ,  Guei-Yuan Lueh ,  Yong Jiang

    IPC分类号： G06T1/60 ,  G06F9/50 ,  G06T1/20 ,  G06F1/32

    CPC分类号： G06T1/60 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F8/451 ,  G06F9/505 ,  G06T1/20 ,  Y02D10/126 ,  Y02D10/152

    摘要： Disclosed methods support dynamic adjustment of graphics processing unit (GPU) frequency. According to one embodiment, a program comprises workload to execute, at least in part, on a GPU of a data processing system. A predetermined memory/compute ratio for the program is automatically retrieved, in response to the program being called for execution. The memory/compute ratio represents a ratio of memory accesses within the program, relative to compute operations within the program. In addition, a frequency of the GPU is automatically adjusted, based on the predetermined memory/compute ratio for the program. For instance, the GPU may be set to a relatively low frequency if the predetermined memory/compute ratio is relatively high, or to a relatively high frequency if the predetermined ratio is relatively low. After the frequency of the GPU is automatically adjusted, the program may execute, at least in part, on the GPU. Other embodiments are described and claimed.

    摘要翻译： 公开的方法支持图形处理单元（GPU）频率的动态调整。 根据一个实施例，程序包括至少部分地在数据处理系统的GPU上执行的工作负载。 响应于要执行的程序，自动检索程序的预定存储器/计算比。 存储器/计算比率表示程序内存储器访问的比率，相对于程序内的计算操作。 此外，基于程序的预定存储器/计算比率，自动调整GPU的频率。 例如，如果预定的存储器/计算比率相对较高，则GPU可以被设置为相对低的频率，或者如果预定比率相对较低，则可以将其设置为相对较低的频率。 在GPU的频率被自动调整之后，该程序可以至少部分地在GPU上执行。 描述和要求保护其他实施例。