公开(公告)号：US20070285730A1

公开(公告)日：2007-12-13

申请号：US11665202

申请日：2005-09-30

申请人： Makoto Suzuki ,  Masaaki Yoshida

发明人： Makoto Suzuki ,  Masaaki Yoshida

IPC分类号： G06K15/00

CPC分类号： H04N1/4076 ,  H04N1/00002 ,  H04N1/00013 ,  H04N1/00031 ,  H04N1/00045 ,  H04N1/0005 ,  H04N1/00063 ,  H04N1/00068 ,  H04N1/00087 ,  H04N1/1912 ,  H04N1/1918 ,  H04N1/401 ,  H04N2201/044

摘要： Photoelectric conversion elements of line sensors (CIS22 to CIS26) arranged in a zigzag manner read a white reference plate to acquire a white reference read value A, and a white reference read average value AA is determined from the white reference read value A for each line sensor. Further, the photoelectric conversion elements read another white reference plate placed on a document support plate to acquire a white reference read value B, and a white reference read average value BB is determined from the white reference read value B for each of the line sensors (CIS22 to CIS26). By using the white reference read average values AA and BB, a sensitivity effect coefficient C used for uniforming the sensitivities different because of the variation of the distances from the line sensors (CIS22 to CIS26) to the document support plate is determined by dividing the average value BB by a data processing section for each of the photoelectric conversion element of the line sensors. By using a white reference read value Aa acquired by reading a white reference plate immediately before reading a document and a black reference read value, a white reference read value Aa for shading correction for correcting a document read value E is corrected with the sensitivity offset coefficient C. In this way, irrespective of the variation of the distances from the line sensors to the document support plate, the variation of the document read values read from the photoelectric conversion element of the line sensors can be suppressed.

摘要翻译： 以Z字形排列的线传感器（CIS22〜CIS26）的光电转换元件读取白色基准板以获取白色基准读取值A，并且从白色基准读取值A确定白色基准读取平均值AA， 每行传感器。 此外，光电转换元件读取放置在原稿支撑板上的另一个白色参考板以获取白色基准读取值B，并且从每个行传感器的白色基准读取值B确定白色基准读取平均值BB（ CIS 22至CIS 26）。 通过使用白色参考读取平均值AA和BB，用于使由于从线路传感器（CIS 22至CIS 26）到文档支撑板的距离的变化而不同的灵敏度的均匀化的灵敏度效应系数C通过分割 平均值BB由行传感器的每个光电转换元件的数据处理部分。 通过使用在读取文档之前通过读取白色参考板获得的白色基准读取值Aa和黑色参考读取值，用灵敏度偏移系数校正用于校正文档读取值E的阴影校正的白色基准读取值Aa 以这种方式，不管从线传感器到文件支撑板的距离的变化如何，可以抑制从线传感器的光电转换元件读取的原稿读取值的变化。

公开(公告)号：US06952035B2

公开(公告)日：2005-10-04

申请号：US10703449

申请日：2003-11-10

申请人： Masaaki Yoshida ,  Hiroaki Nakanishi

发明人： Masaaki Yoshida ,  Hiroaki Nakanishi

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

摘要： A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.

摘要翻译： 非易失性存储器半导体器件包括第一绝缘层，两个扩散区域，存储栅极氧化物层，第一控制栅极，第二绝缘层，多晶硅浮置栅极，第三绝缘层和第二控制栅极。 第一绝缘层形成在半导体衬底上。 两个扩散区形成在基板的表面上。 存储栅极氧化层形成在衬底上的两个扩散区上。 包括扩散区域的第一控制栅极形成在基板的表面上。 第二绝缘层形成在第一控制栅极上。 多晶硅的浮栅形成在存储栅极氧化物层，第一绝缘层和第二绝缘层上。 第三绝缘层形成在浮动栅上。 第二控制栅极设置在浮动栅极上。

公开(公告)号：US5680158A

公开(公告)日：1997-10-21

申请号：US944079

申请日：1992-09-11

申请人： Masaaki Yoshida ,  Isamu Shimoda ,  Mikiharu Matsuoka ,  Yasuko Miyazaki ,  Masaaki Kanashiki

发明人： Masaaki Yoshida ,  Isamu Shimoda ,  Mikiharu Matsuoka ,  Yasuko Miyazaki ,  Masaaki Kanashiki

IPC分类号： H03M11/14 ,  G06F3/023 ,  G06F17/22 ,  G09B5/04 ,  G09B19/06 ,  G09B21/00 ,  G09G5/00 ,  B41J5/00 ,  G09G3/20 ,  H04Q3/00

CPC分类号： G09B5/04 ,  G09B19/06 ,  G09B21/00

摘要： A communication apparatus for a handicapped person, includes a plurality of first key switches for inputting character input data in a general input mode, a single second key switch for inputting character input data in a second key input mode, a character input device for inputting the character input data in the general input mode inputted by operating the plurality of first key switches or in the single key input mode inputted by operating the single second key switch, a character output device for outputting at least character output data which corresponds to the character input data inputted by the character input device, a mode selector for selecting the character input data input in the general input mode by the character input device or the character input data input in the single key input mode by the character input device, and a controller for controlling the operation of the character input device, the character output device, and the input mode selector.

摘要翻译： 用于残疾人的通信装置包括用于以一般输入模式输入字符输入数据的多个第一键开关，用于以第二键输入模式输入字符输入数据的单个第二键开关，用于输入字符输入装置 通过操作多个第一按键开关输入的一般输入模式中的字符输入数据或通过操作单个第二键开关输入的单键输入模式中的字符输入数据，至少输出与字符输入对应的字符输出数据的字符输出装置 由字符输入装置输入的数据，用于通过字符输入装置选择在一般输入模式中输入的字符输入数据的模式选择器或由字符输入装置以单键输入模式输入的字符输入数据的控制器， 控制字符输入装置，字符输出装置和输入模式选择器的操作。

公开(公告)号：US5519714A

公开(公告)日：1996-05-21

申请号：US154206

申请日：1993-11-18

申请人： Yoshiyuki Nakamura ,  Masaaki Yoshida

发明人： Yoshiyuki Nakamura ,  Masaaki Yoshida

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/00

CPC分类号： G01R31/318541 ,  G01R31/318552

摘要： A logic circuit associated with a scan path circuit includes at least one clock controller and at least one scan flipflop. The clock controller includes a first control gate receiving a clock signal and a scan mode signal and configured to maintain its output at a fixed value when the scan mode signal is active, a second control gate receiving an output of the first control gate and a first test clock signal for generating a first enable signal, and a third control gate receiving an output of the second control gate and a second test clock signal for generating a second enable signal. The scan flipflop includes a selector having a pair of inputs receiving a data input signal and a scan input signal, respectively, and also having a selection input receiving the scan mode signal so that when the scan mode signal is active, the scan input signal is selected, and when the scan mode signal is inactive, the data input signal is selected. A first latch circuit receives an output of the selector at its data input and the first enable signal at its enable terminal. A second latch circuit receives an output of the first latch circuit at its data input and the second enable signal at its enable terminal.

摘要翻译： 与扫描路径电路相关联的逻辑电路包括至少一个时钟控制器和至少一个扫描触发器。 时钟控制器包括接收时钟信号和扫描模式信号的第一控制栅极，并且被配置为当扫描模式信号有效时将其输出保持在固定值，第二控制栅极接收第一控制栅极的输出和第一控制栅极 用于产生第一使能信号的测试时钟信号，以及接收第二控制栅极的输出的第三控制栅极和用于产生第二使能信号的第二测试时钟信号。 扫描触发器包括具有分别接收数据输入信号和扫描输入信号的一对输入的选择器，并且还具有接收扫描模式信号的选择输入，使得当扫描模式信号有效时，扫描输入信号为 并且当扫描模式信号无效时，选择数据输入信号。 第一锁存电路在其数据输入端接收选择器的输出，并在其使能端接收第一使能信号。 第二锁存电路在其数据输入端接收第一锁存电路的输出，并在其使能端接收第二使能信号。

公开(公告)号：US5514895A

公开(公告)日：1996-05-07

申请号：US395997

申请日：1995-02-28

申请人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

发明人： Ken'ichi Kikushima ,  Masaaki Yoshida ,  Shinobu Yabuki

IPC分类号： H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L23/53257 ,  H01L23/485 ,  H01L23/5286 ,  H01L24/06 ,  H01L27/0207 ,  H01L2224/05554 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14

摘要： In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.

公开(公告)号：US4713107A

公开(公告)日：1987-12-15

申请号：US940203

申请日：1986-12-10

申请人： Masaaki Yoshida ,  Shigeki Endo ,  Shigeru Kisanuki ,  Hideo Kakuzen

发明人： Masaaki Yoshida ,  Shigeki Endo ,  Shigeru Kisanuki ,  Hideo Kakuzen

IPC分类号： C03B37/018 ,  C03B19/14 ,  C03B37/014 ,  C03B37/12 ,  G02B6/00

CPC分类号： C03B37/0144

摘要： An apparatus is provided for the production of a porous preform of SiO.sub.2 used in the manufacture of optical fiber wherein damage to the preform caused by falling clusters of SiO.sub.2 or GeO.sub.2 formed on the wall of the deposition chamber is eliminated. In accordance with the invention, a conductive shielding member is provided inside the wall defining the deposition chamber. This shielding member eliminates an electrostatic field produced on the wall by charging, therefore preventing the adherence of fine particles thereto.

摘要翻译： 提供了一种用于制造用于制造光纤的多孔预制件的设备，其中消除了由形成在沉积室的壁上形成的SiO 2或GeO 2的下落的团簇引起的对预制件的损伤。 根据本发明，导电屏蔽构件设置在限定沉积室的壁的内部。 该屏蔽构件通过充电消除了在壁上产生的静电场，从而防止了细颗粒附着。

公开(公告)号：US4672614A

公开(公告)日：1987-06-09

申请号：US683446

申请日：1984-12-19

申请人： Masaaki Yoshida

发明人： Masaaki Yoshida

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/42

CPC分类号： G06F11/1008 ,  G06F11/1076

摘要： An improved error-correction type semiconductor memory device operates at high speed. The memory is provided with a pair of row address buffers which can operate independently, and when error correcting operation is performed for the data related to the address contents of one of the buffers, the access operation of the data cell array is conducted by the other of the buffers, thereby enabling the memory device to simultaneously carry out parts of the operation of successive read-out operations.

摘要翻译： 改进的纠错型半导体存储器件以高速操作。 存储器设置有可以独立操作的一对行地址缓冲器，并且当对与缓冲器之一的地址内容相关的数据执行纠错操作时，数据单元阵列的访问操作由另一个执行 从而使存储器件能够同时执行连续读出操作的部分操作。

公开(公告)号：US4610525A

公开(公告)日：1986-09-09

申请号：US758842

申请日：1985-07-25

申请人： Masaaki Yoshida ,  Hiroyuki Kataoka

发明人： Masaaki Yoshida ,  Hiroyuki Kataoka

IPC分类号： G03B15/05 ,  G03B7/097

CPC分类号： G03B15/05 ,  G03B2215/055

摘要： In a flash device arranged to determine the aperture value of a photo-taking lens according to the measured level of a reflection light obtained by preliminary flashing and to control main flashing according to a light control level corresponding to the aperture value, when a light diffusing panel is arranged in front of a main flashing part for a wider flash illuminating angle, another light diffusing panel which gives an equal light reducing effect is also arranged for a preliminary flashing part. The light quantity of preliminary flashing is thus reduced in proportion to the degree of reduction in the light quantity of main flashing, so that the aperture value set by preliminary flashing and the light controllable range of main flashing for photographing can be made to be always in agreement with each other.

摘要翻译： 在闪光灯装置中，其被配置为根据通过预备闪光获得的反射光的测量水平来确定摄影镜头的光圈值，并且根据与光圈值对应的光控制水平来控制主闪光，当光扩散 面板布置在主闪光部分的前面，用于更宽的闪光照明角度，还为初步闪光部分布置另外具有相同减光效果的光漫射板。 预先闪光的光量与主闪光量的减少程度成比例地减小，从而可以使通过初步闪光设定的光圈值和用于拍摄的主闪光的光可控范围始终保持在 相互约定

公开(公告)号：US4208252A

公开(公告)日：1980-06-17

申请号：US683153

申请日：1976-05-04

申请人： Masaaki Yoshida ,  Masao Watanabe ,  Kimio Tohma ,  Mitsuhiko Noda

发明人： Masaaki Yoshida ,  Masao Watanabe ,  Kimio Tohma ,  Mitsuhiko Noda

IPC分类号： C10B47/44 ,  C10B53/00 ,  C10B53/07 ,  C10B1/06 ,  C10B1/08 ,  C10B27/00

CPC分类号： C10B47/44 ,  C10B53/07 ,  Y02P20/143

摘要： An apparatus for treatment of rubber and plastic wastes, comprising in series an extruder for heating and melting rubber and plastic wastes to extrude the molten wastes, a decomposing section for heating the molten wastes to prepare decomposed products while optionally separating residues therefrom, a dry-distilling section for gasifying the decomposed products by dry-distillation, and a cooling section for cooling the dry-distilled products to separate gaseous materials from liquid materials.

摘要翻译： 一种用于处理橡胶和塑料废物的设备，包括用于加热和熔化橡胶和塑料废料以挤出熔融废物的挤出机，用于加热熔融废物以制备分解产物同时任选分离残余物的分解部分， 用于通过干馏气化分解产物的蒸馏部分，以及用于冷却干蒸馏产物以将液体材料与液体材料分离的冷却部分。

公开(公告)号：US11035901B2

公开(公告)日：2021-06-15

申请号：US15581311

申请日：2017-04-28

申请人： Masaaki Yoshida

发明人： Masaaki Yoshida

IPC分类号： G01R31/364 ,  G01R31/36 ,  G01R31/392

摘要： A state output apparatus includes a power storage device information acquirer configured to acquire power storage device information including a voltage and a current of a power storage device; an integrated current amount calculator configured to calculate an integrated current amount supplied to the power storage device during a period in which the voltage changes from a first voltage to a second voltage between a discharge end voltage and a charge end voltage by charging the power storage device; an integrated current amount comparer configured to compare the calculated integrated current amount with a reference integrated current amount stored in a storage device; and a state outputter configured to output a result of the comparison as information indicating a state of the power storage device.