公开(公告)号：US06774033B1

公开(公告)日：2004-08-10

申请号：US10287258

申请日：2002-11-04

Applicant: Mira Ben-Tzur ,  Dafna Beery ,  Gorley L. Lau ,  Krishnaswamy Ramkumar

Inventor： Mira Ben-Tzur ,  Dafna Beery ,  Gorley L. Lau ,  Krishnaswamy Ramkumar

IPC: H01L214763

CPC classification number: H01L21/32051 ,  H01L21/76895

Abstract: In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.

Abstract translation: 在一个实施例中，通过在氧化物层上沉积第一膜并在第一膜上沉积第二膜来形成集成电路中的局部互连层。 第一膜可以包括氮化钛，而第二膜可以包括例如钨。 第一膜和第二膜可以通过溅射原位沉积。 可以使用第一膜作为蚀刻停止来蚀刻第二膜，并且可以使用氧化物层作为蚀刻停止来蚀刻第一膜。

公开(公告)号：US09023707B1

公开(公告)日：2015-05-05

申请号：US13312964

申请日：2011-12-06

Applicant: Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

Inventor： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick B. Jenne

IPC: H01L21/336 ,  H01L21/768

CPC classification number: H01L21/768 ,  H01L27/11568 ,  H01L29/792

Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.

Abstract translation: 提供了ONO集成到MOS流中的方法。 在一个实施例中，该方法包括：（i）在衬底的MOS器件区域的上方形成焊盘电介质层; 并且（ii）在衬底的非易失性器件区域之上形成图案化的电介质堆叠，所述图案化的电介质叠层包括隧道层，电荷俘获层和牺牲顶层，所述电荷俘获层包括多个层，包括 形成在隧道层上的第一氮化物层和第二氮化物层，其中第一氮化物层相对于第二氮化物层富氧。 还描述了其它实施例。

公开(公告)号：US08822349B1

公开(公告)日：2014-09-02

申请号：US13401712

申请日：2012-02-21

Applicant: Jeong Soo Byun ,  Krishnaswamy Ramkumar

Inventor： Jeong Soo Byun ,  Krishnaswamy Ramkumar

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02323 ,  H01L21/02326

Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.

Abstract translation: 提供制造半导体结构的方法。 该方法包括使用高密度等离子体氧化工艺形成介电层。 电介质层在存储层上，并且在高密度等离子体氧化过程中存储层的厚度减小。

公开(公告)号：US08685813B2

公开(公告)日：2014-04-01

申请号：US13428201

申请日：2012-03-23

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/8238

CPC classification number: H01L27/11573 ,  H01L21/28282 ,  H01L21/823462 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/792

Abstract: Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed.

Abstract translation: 描述了将非易失性存储器件集成到MOS流中的方法的实施例。 通常，所述方法包括：在衬底的表面上形成电介质叠层，所述电介质堆叠包括覆盖所述衬底表面的隧道电介质和覆盖所述隧道电介质的电荷捕获层; 形成覆盖在所述电介质叠层上的盖层; 图案化所述盖层和所述电介质堆叠以在所述衬底的第一区域中形成存储器件的栅极叠层，并且从所述衬底的第二区域去除所述覆盖层和所述电荷俘获层; 以及进行氧化处理，以形成覆盖在第二区域中的衬底的表面上的MOS器件的栅极氧化物，同时对盖层进行氧化以形成覆盖电荷俘获层的阻挡氧化物。 还公开了其他实施例。

公开(公告)号：US20080296661A1

公开(公告)日：2008-12-04

申请号：US12185747

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

Inventor： Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US06902993B2

公开(公告)日：2005-06-07

申请号：US10402750

申请日：2003-03-28

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar ,  Prabhuram Gopalan

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar ,  Prabhuram Gopalan

IPC: H01L21/28 ,  H01L21/324 ,  H01L29/49 ,  H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/4941 ,  H01L21/28052 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/78

Abstract: In one embodiment, a gate of a transistor is formed by performing a first thermal treatment on a silicon layer, forming a metal stack over the silicon layer, and performing a second thermal treatment on the metal stack. The first thermal treatment may be a rapid thermal annealing step, while the second thermal treatment may be a rapid thermal nitridation step. The resulting gate exhibits relatively low interface contact resistance between the silicon layer and the metal stack, and may thus be advantageously employed in high-speed devices.

Abstract translation: 在一个实施例中，通过在硅层上进行第一热处理，在硅层上形成金属堆叠，并在金属堆上进行第二热处理，形成晶体管的栅极。 第一热处理可以是快速热退火步骤，而第二热处理可以是快速热氮化步骤。 所得到的栅极在硅层和金属堆叠之间表现出相对较低的界面接触电阻，因此可有利地用于高速器件中。

公开(公告)号：US20050067663A1

公开(公告)日：2005-03-31

申请号：US10950332

申请日：2004-09-24

Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01L21/28 ,  H01L21/314 ,  H01L29/49 ,  H01L29/78 ,  H01L21/20

CPC classification number: H01L21/022 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02337 ,  H01L21/28044 ,  H01L21/3144 ,  H01L29/4941 ,  H01L29/78

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract translation: 制造半导体结构的方法包括在衬底上形成氧化物层; 在氧化物层上形成氮化硅层; 在NO中退火层; 并在氨中退火层。 氧化物层和氮化硅层的等效氧化物厚度在一起为至多25埃。

公开(公告)号：US06841491B1

公开(公告)日：2005-01-11

申请号：US10039469

申请日：2001-11-08

Applicant: Sharmin Sadoughi ,  Krishnaswamy Ramkumar

Inventor： Sharmin Sadoughi ,  Krishnaswamy Ramkumar

IPC: H01L21/027 ,  H01L21/318 ,  H01L21/31

CPC classification number: H01L21/0276 ,  H01L21/3185

Abstract: A process for fabricating a semiconductor structure comprises depositing a nitride layer on a semiconductor substrate with a first tool, and depositing an anti-reflective layer on the semiconductor substrate with the first tool. The nitride layer includes silicon and nitrogen.

Abstract translation: 一种用于制造半导体结构的工艺包括用第一工具在半导体衬底上沉积氮化物层，并在第一工具上在半导体衬底上沉积抗反射层。 氮化物层包括硅和氮。

公开(公告)号：US06838392B1

公开(公告)日：2005-01-04

申请号：US10119574

申请日：2002-04-09

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/02052 ,  H01L21/31111 ,  H01L21/76232

Abstract: A method of forming a semiconductor structure is described that includes etching a trench in a semiconductor substrate, wherein an oxide layer overlies the semiconductor substrate, and a nitride layer overlies the oxide layer; and cleaning the semiconductor substrate while simultaneously performing a pull back of the nitride layer. Methods of making semiconductor devices and electronic devices, and silicon wafers having trenches and isolation regions formed by the above-mentioned methods are also described.

公开(公告)号：US06818558B1

公开(公告)日：2004-11-16

申请号：US10185470

申请日：2002-06-28

Applicant: Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

Inventor： Manuj Rathor ,  Krishnaswamy Ramkumar ,  Fred Jenne ,  Loren Lancaster

IPC: H01L21311

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/7882

Abstract: A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step 102), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step 104), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step 106).

Abstract translation: 公开了形成电荷存储层的方法。 根据实施例，一种方法可以包括以第一气体流速比形成电荷存储层的第一部分（步骤102）的步骤，通过改变到第二气体形成电荷存储层的至少第二部分 流量比与第一气体流量比不同（步骤104），并且通过改变到与第二气体流量比不同的第三气体流量比形成至少第三部分的电荷存储层（ 步骤106）。