Driver with electrostatic discharge protection
    51.
    发明授权
    Driver with electrostatic discharge protection 有权
    驱动器具有静电放电保护

    公开(公告)号:US07855863B2

    公开(公告)日:2010-12-21

    申请号:US12274085

    申请日:2008-11-19

    CPC分类号: H02H9/046

    摘要: Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.

    摘要翻译: 本文公开了用于保护驾驶员免受静电放电的各种装置,方法和系统。 例如,一些示例性实施例提供了包括缓冲器的驱动器,连接到缓冲器的输出的泄漏路径阻塞晶体管,以及连接到泄漏路径阻挡晶体管的输出的输出驱动器。 从输出驱动器到缓冲器的电流基本上被泄漏路径阻断晶体管阻挡。

    Fast transition from low-speed mode to high-speed mode in high-speed interfaces
    52.
    发明授权
    Fast transition from low-speed mode to high-speed mode in high-speed interfaces 有权
    在高速接口中从低速模式快速转换到高速模式

    公开(公告)号:US07752476B2

    公开(公告)日:2010-07-06

    申请号:US11804413

    申请日:2007-05-17

    IPC分类号: G01R31/28

    摘要: Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.

    摘要翻译: 描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。 在用于高速接口的低速到高速转换操作模式期间,存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号,并且与低速接口的继续操作同时进行 模式。 参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作,允许相位检测和校正电路被禁用,从而允许由 从低速模式向高速模式的转变将大大降低。

    ION-EXCHANGE DEVICE AND REGENERATION METHOD OF ION-EXCHANGE MATERIAL THEREOF
    53.
    发明申请
    ION-EXCHANGE DEVICE AND REGENERATION METHOD OF ION-EXCHANGE MATERIAL THEREOF 有权
    离子交换装置及其交换材料的再生方法

    公开(公告)号:US20100147704A1

    公开(公告)日:2010-06-17

    申请号:US12336792

    申请日:2008-12-17

    IPC分类号: C02F1/461 C02F1/42

    摘要: An electrochemical device comprises an electrochemical cell. The electrochemical cell comprises a composite cation-exchange member including a conductive base and a cation-exchange material in physical contact with the conductive base, a composite anion-exchange member including a conductive base and an anion-exchange material in physical contact with the conductive base; and a compartment between the composite cation-exchange and anion-exchange members. The compartment comprises an inlet for introducing a feed stream, and an outlet for exiting of an output stream out of the compartment. The electrochemical device comprises a control device configured to transmit an electrical current to the composite cation-exchange and anion-exchange members at a regeneration stage in a manner that the conductive base on the composite cation-exchange member loses electrons and the conductive base on the composite anion-exchange member gains electrons.

    摘要翻译: 电化学装置包括电化学电池。 所述电化学电池包括复合阳离子交换部件,所述复合阳离子交换部件包括与所述导电性基体物理接触的导电性基体和阳离子交换材料,所述复合阴离子交换部件包含与导电性物理接触的导电性碱和阴离子交换材料 基础; 和复合阳离子交换和阴离子交换构件之间的隔室。 隔室包括用于引入进料流的入口和用于将输出流离开隔室的出口。 电化学装置包括控制装置,其被配置为以再生阶段的方式将复合阳离子交换和阴离子交换构件的电流传递到复合阳离子交换构件上的导电性基底上,并且导电性基底 复合阴离子交换元件获得电子。

    SYSTEM AND METHOD FOR INSTRUCTION LATENCY REDUCTION IN GRAPHICS PROCESSING
    55.
    发明申请
    SYSTEM AND METHOD FOR INSTRUCTION LATENCY REDUCTION IN GRAPHICS PROCESSING 有权
    图形处理中的指令减少的系统和方法

    公开(公告)号:US20090213128A1

    公开(公告)日:2009-08-27

    申请号:US12035667

    申请日:2008-02-22

    申请人: Lin Chen

    发明人: Lin Chen

    IPC分类号: G06F15/16

    CPC分类号: G06F8/443 G06F8/445

    摘要: A system, method and apparatus are disclosed, in which an instruction scheduler of a compiler, e.g., a shader compiler, reduces instruction latency based on a determined instruction distance between a dependent predecessor and successor instructions.

    摘要翻译: 公开了一种系统,方法和装置,其中编译器的指令调度器(例如,着色器编译器)基于从属前导和后继指令之间的确定的指令距离来减少指令等待时间。

    Methods for the synthesis of cyclic peptides
    58.
    发明申请
    Methods for the synthesis of cyclic peptides 审中-公开
    合成环肽的方法

    公开(公告)号:US20080287649A1

    公开(公告)日:2008-11-20

    申请号:US12004265

    申请日:2007-12-20

    IPC分类号: C07K2/00 C07C69/616 C07K5/12

    摘要: Methods for the synthesis of cyclic peptides are provided, as well as novel dipeptide compounds. The methods include the solid phase synthesis of a dipeptide, which is the coupled to a second peptide in a solid phase reaction. The peptide is then cyclized following the coupling reaction. The methods and dipeptides are particularly useful for the synthesis of MC-4 receptor agonist peptides.

    摘要翻译: 提供了合成环肽的方法,以及新型二肽化合物。 所述方法包括在固相反应中与第二肽偶联的二肽的固相合成。 然后在偶合反应后使肽环化。 该方法和二肽特别可用于合成MC-4受体激动剂肽。

    METHOD, SYSTEM AND DEVICE FOR IMPROVING COMMUNICATION QUALITY IN CDMA SYSTEM
    59.
    发明申请
    METHOD, SYSTEM AND DEVICE FOR IMPROVING COMMUNICATION QUALITY IN CDMA SYSTEM 有权
    用于改善CDMA系统中通信质量的方法,系统和设备

    公开(公告)号:US20070218909A1

    公开(公告)日:2007-09-20

    申请号:US11743448

    申请日:2007-05-02

    申请人: Ailin Deng Lin Chen

    发明人: Ailin Deng Lin Chen

    IPC分类号: H04Q7/20

    CPC分类号: H04W16/00 H04B1/707

    摘要: A method for improving communication quality in a CDMA system includes: storing, groups of quality control parameters for a BS covered by the BSC; adopting, by the BS and an MS covered by the BS, one of the groups of the quality control parameters to interact with each other when the MS sets up a call; monitoring, during the call, communication quality parameters reported by the BS or by the MS; and selecting one of the groups of the quality control parameters according to the communication quality parameters and transmitting the group of the quality control parameters selected to the BS or the MS. A system and a BSC are also disclosed by the embodiments of the present invention. The solution provided by the embodiments of the present invention may improve the communication quality in areas with weak signals.

    摘要翻译: 一种用于提高CDMA系统中的通信质量的方法包括:存储由BSC覆盖的BS的质量控制参数组; 当MS建立呼叫时,由BS和MS所涵盖的MS采用质量控制参数的组之一进行交互; 在通话期间监视由BS或MS报告的通信质量参数; 以及根据所述通信质量参数选择所述质量控制参数组中的一组,并将选择的所述质量控制参数的组发送给所述BS或所述MS。 本发明的实施例也公开了系统和BSC。 由本发明实施例提供的解决方案可以改善弱信号区域的通信质量。

    Dynamic impedance compensation circuit and method
    60.
    发明授权
    Dynamic impedance compensation circuit and method 有权
    动态阻抗补偿电路及方法

    公开(公告)号:US07227376B2

    公开(公告)日:2007-06-05

    申请号:US10982485

    申请日:2004-11-05

    IPC分类号: H03K17/16 H03K19/003

    CPC分类号: H03K19/0005

    摘要: An impedance compensation circuit generates per-group pull-up impedance information and per-group pull-down impedance information to calibrate a plurality of input/output pads and dynamically updates impedance information on a per channel basis. A group refers to a group of I/O pads having similar output drive strengths in a channel. A channel refers to all I/O pads, which collectively provide a bus interface to an external device. For example, all the I/O pads interfacing with a memory module may be grouped into a channel, and address I/O pads in a channel may be arranged into a “group.” Memory I/O pads may be grouped together into a channel since memory interface pads have input/output characteristics that may be different from those of other types of I/O pads in the chip. According to one embodiment, per-group programmable offset information provides calibration information that may be different for each group in each channel.

    摘要翻译: 阻抗补偿电路产生每组上拉阻抗信息和每组下拉阻抗信息以校准多个输入/输出焊盘,并基于每个通道动态地更新阻抗信息。 组是指在通道中具有相似输出驱动强度的一组I / O焊盘。 一个通道是指所有的I / O焊盘,它们共同地为外部设备提供总线接口。 例如,与存储器模块接口的所有I / O焊盘可以分组成通道,并且通道中的地址I / O焊盘可以被布置成“组”。 存储器I / O焊盘可以被组合在一起成为通道,因为存储器接口焊盘具有与芯片中的其它类型的I / O焊盘的输入/输出特性不同的输入/输出特性。 根据一个实施例,每组可编程偏移信息提供对于每个通道中的每个组可以不同的校准信息。