公开(公告)号：US20090180237A1

公开(公告)日：2009-07-16

申请号：US12410117

申请日：2009-03-24

申请人： Cliff Hou ,  Lee-Chung Lu ,  Chia-Lin Cheng

发明人： Cliff Hou ,  Lee-Chung Lu ,  Chia-Lin Cheng

IPC分类号： H01G4/228

CPC分类号： H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

摘要翻译： 公开了一种在集成电路中使用虚设导电元件的去耦合电容器模块。 解耦模块包括具有一个或多个有源节点的至少一个电路模块和未连接到任何有源节点的至少一个虚拟导电元件，并且通过绝缘区域与高压导体或低压导体分离，以提供 去耦合电容。

公开(公告)号：US07262951B2

公开(公告)日：2007-08-28

申请号：US10952259

申请日：2004-09-27

申请人： Cliff Hou ,  Lee-Chung Lu ,  Chia-Lin Cheng

发明人： Cliff Hou ,  Lee-Chung Lu ,  Chia-Lin Cheng

IPC分类号： H01G4/228

CPC分类号： H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A de-coupling capacitor module using dummy conductive elements in an integrated circuit is disclosed. The de-coupling module comprises at least one circuit module having one or more active nodes, and at least one dummy conductive element unconnected to any active node, and separated from a high voltage conductor or a low voltage conductor by an insulation region to provide a de-coupling capacitance.

摘要翻译： 公开了一种在集成电路中使用虚设导电元件的去耦合电容器模块。 解耦模块包括具有一个或多个有源节点的至少一个电路模块和未连接到任何有源节点的至少一个虚拟导电元件，并且通过绝缘区域与高电压导体或低压导体分离，以提供 去耦合电容。

公开(公告)号：US20070158835A1

公开(公告)日：2007-07-12

申请号：US11332566

申请日：2006-01-12

申请人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

发明人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

IPC分类号： H01L23/48

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.

摘要翻译： 公开了一种用于在从参考处理技术缩放到预定处理技术的同时，分别在集成电路的两层中确定第一和第二导体之间的互连尺寸的方法。 该方法包括基于预定的处理技术来选择一组导体的设计规则，基于设计规则确定互连的矩形横截面积的第一侧的长度，以及用于缩放这种长度的缩放规则 将参考处理技术应用于预定处理技术，以及确定互连横截面积的第二侧的长度，以补偿由于从参考处理技术到预定处理技术的缩放而导致的互连电阻的增加 。

公开(公告)号：US20070109832A1

公开(公告)日：2007-05-17

申请号：US11281035

申请日：2005-11-17

申请人： Yung-Chin Hou ,  Lee-Chung Lu ,  Chu-Ping Wang ,  Li-Chun Tien

发明人： Yung-Chin Hou ,  Lee-Chung Lu ,  Chu-Ping Wang ,  Li-Chun Tien

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  H01L27/0207

摘要： A semiconductor structure includes a first conductive line for connecting to a power supply, and a second conductive line for connecting to a complementary power supply. At least one spare cell is decoupled from the first or second conductive line for being selectively connected to at lease one normal cell, the first conductive line and the second conductive line only when an engineering change order is placed.

摘要翻译： 半导体结构包括用于连接到电源的第一导线和用于连接到互补电源的第二导线。 至少一个备用单元与第一或第二导线分离，以便仅当放置工程改变顺序时才有选择地连接到至少一个正常单元，第一导线和第二导线。

公开(公告)号：US06789248B1

公开(公告)日：2004-09-07

申请号：US10178401

申请日：2002-06-24

申请人： Lee-Chung Lu ,  Cliff Hou ,  Chia-Lin Cheng ,  Chung-Hsing Wang ,  Hsing-Chien Huang ,  Yee-Wen Chen ,  Tsui-Ping Wang

发明人： Lee-Chung Lu ,  Cliff Hou ,  Chia-Lin Cheng ,  Chung-Hsing Wang ,  Hsing-Chien Huang ,  Yee-Wen Chen ,  Tsui-Ping Wang

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method and system for the design of an electronic device adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits. The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines the delay created by the component circuit and the networks of physical wire segments. The time delay resulting from the physical interconnects is extracted from the timing analysis of the electronic device and from the timing estimate performed during the physical synthesis. The time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis is then compared. The resistance and capacitance unit values used during the timing synthesis are then adjusted. The calibration is repeatedly executed until time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis are correlated.

摘要翻译： 用于设计电子设备的方法和系统调节在电子设备的物理合成期间的初步时序分析中使用的电阻和电容值。 物理合成使用电阻和电容单位值来确定元件电路的列表。 电阻和电容单位值通过预先放置最初合成的组件电路来校准，以创建描述电子设备内的组件电路的物理位置的列表。 执行互连的初步路由以创建描述形成组件电路的每个互连的物理线段的网络的列表。 电子设备的定时分析确定由组件电路和物理线段网络产生的延迟。 从物理互连产生的时间延迟从电子设备的定时分析以及在物理合成期间执行的定时估计提取。 然后对来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计进行比较。 然后调整在定时合成期间使用的电阻和电容单位值。 重复执行校准，直到来自定时分析的物理互连的时间延迟和在物理合成期间执行的定时估计相关。

公开(公告)号：US09672315B2

公开(公告)日：2017-06-06

申请号：US12846594

申请日：2010-07-29

申请人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

发明人： Lee-Chung Lu ,  Yi-Kan Cheng ,  Chung-Hsing Wang ,  Chen-Fu “Alex” Huang ,  Hsiao-Shu Chao ,  Chin-Yu Chiang ,  Ho Che Yu ,  Chih Sheng Tsai ,  Shu Yi Ying

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072

摘要： An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.

公开(公告)号：US09608604B2

公开(公告)日：2017-03-28

申请号：US11639006

申请日：2006-12-14

申请人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

发明人： Lee-Chung Lu ,  Chung-Hsing Wang ,  Chun-Hui Tai ,  Li-Chun Tien ,  Shun-Li Chen

IPC分类号： H03L5/00 ,  H03K3/356

CPC分类号： H03K3/35613

摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

公开(公告)号：US08607172B2

公开(公告)日：2013-12-10

申请号：US13267310

申请日：2011-10-06

申请人： Lee-Chung Lu ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Mei-Hui Huang

发明人： Lee-Chung Lu ,  Li-Chun Tien ,  Hui-Zhong Zhuang ,  Mei-Hui Huang

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  G06F17/5077 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11885

摘要： A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.

摘要翻译： 设计集成电路的方法包括在第一标准单元中部署有效区域。 至少一个栅电极被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构被路由，与第一标准单元中的有效区重叠。 至少一个金属线结构基本上平行于栅电极。 第一电源轨道基本上正交于第一标准单元中的至少一个金属线结构。 第一电力轨与至少一个金属线结构重叠。 第一动力轨具有与至少一个金属线结构相邻的平坦边缘。 第一连接插头部署在第一电力轨道与第一标准单元中的至少一个金属线结构重叠的区域处。

公开(公告)号：US08584052B2

公开(公告)日：2013-11-12

申请号：US13084255

申请日：2011-04-11

申请人： Huang-Yu Chen ,  Yuan-Te Hou ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

发明人： Huang-Yu Chen ,  Yuan-Te Hou ,  Ken-Hsien Hsieh ,  Ru-Gun Liu ,  Lee-Chung Lu

IPC分类号： G06F17/50

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70466

摘要： A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell.

摘要翻译： 提供了一种用于提供用于多个图案化技术的单元布局的系统和方法。 要被图案化的区域被分成对应于各种掩模的交替位置。 在布局过程中，沿着单元边界定位的站点被限制为具有与边界站点相关联的掩码中的模式。 当放置时，各个单元被布置成使得相邻的单元交替分配给各种掩模的位置。 以这种方式，设计者知道在设计每个单独的单元时，一个单元的掩模图案将太靠近相邻单元的掩模图案。

公开(公告)号：US08504972B2

公开(公告)日：2013-08-06

申请号：US12697887

申请日：2010-02-01

申请人： Yung-Chin Hou ,  David Barry Scott ,  Lee-Chung Lu ,  Li-Chun Tien

发明人： Yung-Chin Hou ,  David Barry Scott ,  Lee-Chung Lu ,  Li-Chun Tien

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： An integrated circuit layout includes a standard cell, which includes a first gate strip and a second gate strip parallel to each other and having a gate pitch; a first boundary and a second boundary on opposite ends of the first standard cell; and a third boundary and a fourth boundary on opposite ends of the first standard cell and parallel to the first gate strip and the second gate strip. A cell pitch between the third boundary and the fourth boundary is not equal to integer times the gate pitch. A PMOS transistor is formed of the first gate strip and a first active region. An NMOS transistor is formed of the first gate strip and a second active region.

摘要翻译： 集成电路布局包括标准单元，其包括彼此平行并具有栅极间距的第一栅极条和第二栅极条; 在第一标准单元的相对端上的第一边界和第二边界; 以及在第一标准单元的相对端上并且平行于第一栅极条和第二栅极条的第三边界和第四边界。 第三边界和第四边界之间的单元间距不等于门间距的整数倍。 PMOS晶体管由第一栅极条和第一有源区形成。 NMOS晶体管由第一栅极条和第二有源区形成。