公开(公告)号：US11562229B2

公开(公告)日：2023-01-24

申请号：US16450334

申请日：2019-06-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G06N3/08 ,  G06N20/10 ,  G06F17/15 ,  G06F17/16

Abstract: A method for accelerating a convolution of a kernel matrix over an input matrix for computation of an output matrix using in-memory computation involves storing in different sets of cells, in an array of cells, respective combinations of elements of the kernel matrix or of multiple kernel matrices. To perform the convolution, a sequence of input vectors from an input matrix is applied to the array. Each of the input vectors is applied to the different sets of cells in parallel for computation during the same time interval. The outputs from each of the different sets of cells generated in response to each input vector are sensed to produce a set of data representing the contributions of that input vector to multiple elements of an output matrix. The sets of data generated across the input matrix are used to produce the output matrix.

公开(公告)号：US11062197B2

公开(公告)日：2021-07-13

申请号：US15803971

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G06N3/04 ,  G06F17/12

Abstract: A neuromorphic computing system includes a synapse array, a switching circuit, a sensing circuit and a processing circuit. The synapse array includes row lines, column lines and synapses. The processing circuit is coupled to the switching circuit and the sensing circuit and is configured to connect a particular column line in the column lines to the first terminal by using the switching circuit, obtain a first voltage value from the particular column line by using the sensing circuit when the particular line is connected to the first terminal, connect the particular column line to the second terminal by using the switching circuit, obtain a second voltage value from the particular column line by using the sensing circuit when the particular line is connected to the second terminal, and estimate a sum-of-product sensing value according to a voltage difference between the first voltage value and the second voltage value.

公开(公告)号：US10528862B1

公开(公告)日：2020-01-07

申请号：US16222222

申请日：2018-12-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee

IPC: G11C16/04 ,  G06N3/02 ,  G11C16/08 ,  H01L29/788 ,  G11C16/26 ,  H01L27/11524 ,  G11C16/10

Abstract: A neural network system includes a doping well having a first conductivity, a memory string having a plurality of memory cells each include a gate and a source/drain with a second conductivity disposed in the doping well, a buried channel layer having the second conductivity and disposed in the doping well, a word line driver used to apply input voltages corresponding to a plurality of input variations of terms in the sum-of-products operations, a voltage sensing circuit used to apply a constant current into the memory string and to sensing a voltage, a controller used to program/read the memory cells for acquiring a plurality of threshold voltages corresponds to weights of the terms in the sum-of-products operations. When programing/reading the threshold voltages, a first bias voltage is applied to the first doping well; and when sensing the voltage, a second bias voltage is applied to the first doping well.

公开(公告)号：US10103895B1

公开(公告)日：2018-10-16

申请号：US15782890

申请日：2017-10-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao Tseng ,  Yu-Yu Lin ,  Kai-Chieh Hsu ,  Feng-Min Lee

IPC: G11C11/00 ,  H04L9/32 ,  G06F21/73 ,  H04L9/08 ,  G11C13/00

Abstract: A method for physically unclonable function-identification (PUF-ID) generation includes: providing a PUF array having programmable resistance memory cells; performing a forming procedure followed by a programming procedure on all of the programmable resistance memory cells of the PUF array; performing an estimation process to estimate randomness of the PUF array, by comparing a reference current of a base unit to a total current passing through all of the programmable resistance memory cells for obtaining a PUF randomness; determining a setting result of randomness based on the estimation process; and generating a PUF-ID according to the setting result of randomness.

公开(公告)号：US09455403B1

公开(公告)日：2016-09-27

申请号：US14838500

申请日：2015-08-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Feng-Min Lee ,  Yu-Yu Lin ,  Dai-Ying Lee

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises an access device, a dielectric layer, a barrier layer, a first interlayer conductor, a first barrier liner, a second interlayer conductor, a second barrier liner, a memory element and a top electrode layer. The access device has two terminals. The dielectric layer covers the access device. The barrier layer is disposed on the dielectric layer. The first and second interlayer conductors are connected to the two terminals, respectively. The first and second barrier liners are disposed on sidewalls of the first and second interlayer conductors, respectively. The memory element is disposed on the first interlayer conductor. The top electrode layer is disposed on the barrier layer and the memory element and covers the memory element.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括存取装置，电介质层，阻挡层，第一层间导体，第一阻挡衬垫，第二层间导体，第二阻挡衬垫，存储元件和顶电极层。 接入设备有两个终端。 电介质层覆盖接入装置。 阻挡层设置在电介质层上。 第一和第二层间导体分别连接到两个端子。 第一和第二阻挡衬垫分别设置在第一和第二层间导体的侧壁上。 存储元件设置在第一层间导体上。 顶部电极层设置在阻挡层和存储元件上并覆盖存储元件。

公开(公告)号：US09455402B2

公开(公告)日：2016-09-27

申请号：US14603390

申请日：2015-01-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Yu Lin ,  Feng-Min Lee ,  Kuang-Hao Chiang ,  Ming-Hsiu Lee

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L45/04 ,  H01L45/124 ,  H01L45/1633

Abstract: A resistive memory device is provided, comprising a bottom electrode, a patterned dielectric layer with a via formed on the bottom electrode, a barrier layer formed at sidewalls and a bottom surface of the via as a liner, a ring-shaped metal layer formed at sidewalls and a bottom surface of the barrier layer, and a ring-shaped metal oxide formed on a top surface of the ring-shaped metal layer.

Abstract translation: 提供了一种电阻式存储器件，包括底部电极，形成在底部电极上的通孔的图案化电介质层，形成在通孔的侧壁和底部表面的阻挡层作为衬垫，形成在环形金属层 侧壁和阻挡层的底表面，以及形成在环形金属层的顶表面上的环形金属氧化物。

公开(公告)号：US09245925B1

公开(公告)日：2016-01-26

申请号：US14598116

申请日：2015-01-15

Applicant: Macronix International Co., Ltd.

Inventor： Feng-Min Lee ,  Erh-Kun Lai ,  Yu-Yu Lin

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L45/1675

Abstract: Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming an insulation layer on an access device followed by forming vias through the insulation layer to expose the first and second access device terminals. First and second interlayer conductors extending through the vias are formed next. Top surfaces of the interlayer conductors are oxidized to form oxide layers. The oxide layer on the first interlayer conductor forms a memory layer. On top of the insulation layer a layer of protection metal is formed covering the oxide layers. The layer of protection metal is patterned and etched to form a top electrode layer covering the memory layer. The oxide layer on the second interlayer conductor is removed. Parallel first and second access lines are then formed on the top electrode layer and the second interlayer conductor, respectively.

Abstract translation: 本文描述了基于金属氧化物的存储器件及其制造方法。 一种用于制造存储单元的方法包括在存取装置上形成绝缘层，随后通过绝缘层形成通孔以暴露第一和第二接入装置终端。 接下来形成穿过通孔延伸的第一和第二层间导体。 层间导体的顶表面被氧化形成氧化物层。 第一层间导体上的氧化物层形成存储层。 在绝缘层的顶部，形成覆盖氧化物层的保护金属层。 保护金属层被图案化和蚀刻以形成覆盖存储层的顶部电极层。 去除第二层间导体上的氧化物层。 然后分别在顶电极层和第二层间导体上形成平行的第一和第二存取线。

公开(公告)号：US09019769B2

公开(公告)日：2015-04-28

申请号：US13710517

申请日：2012-12-11

Applicant: Macronix International Co., Ltd.

Inventor： Feng-Ming Lee ,  Yu-Yu Lin ,  Ming-Hsiu Lee

IPC: G11C16/04 ,  H01L29/788 ,  H01L21/28

CPC classification number: G11C16/0408 ,  H01L21/28273 ,  H01L29/788

Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped region is in the substrate. The stack structure is on the substrate. The stack structure comprises a dielectric layer, an electrode layer, a solid electrolyte layer and an ion supplying layer.

Abstract translation: 提供了一种半导体器件及其制造方法及其操作方法。 半导体器件包括衬底，掺杂区域和堆叠结构。 掺杂区域在衬底中。 堆叠结构在衬底上。 堆叠结构包括电介质层，电极层，固体电解质层和离子供给层。