公开(公告)号：US10826393B2

公开(公告)日：2020-11-03

申请号：US16100070

申请日：2018-08-09

Applicant: MediaTek Inc.

Inventor： Yueh-Min Chen ,  Yu-Hsin Lin

IPC: H02M3/158 ,  H02M3/07 ,  H02M1/08 ,  H02M3/156 ,  H02M1/00

Abstract: Direct current-direct current (DC-DC) converters including buck converters are described. These DC-DC converters may be configured to reduce oscillations that would otherwise arise in the output reference voltage due to ringing effects without significantly lengthening the duration of the transient period. These DC converters may leverage a feedback voltage generated by sensing the current flowing through the inductor of the buck converter. The feedback voltage may compared to a threshold, and the signal resulting from the comparison may be used to vary the reference voltage. The DC-DC converter may be operated in a “partial reset mode,” in which the voltage generated by sensing the inductor's current is reduced to a value greater than zero in response to the feedback voltage reaching the threshold. Reducing the sense voltage in this manner may reduce the duration of the transient period.

公开(公告)号：US09806703B2

公开(公告)日：2017-10-31

申请号：US15338628

申请日：2016-10-31

Applicant: MediaTek Inc.

Inventor： Yu-Hsin Lin ,  Tze-Chien Wang

IPC: H03L5/00 ,  H03K5/02

CPC classification number: H03K5/02 ,  H03F1/26 ,  H03F3/26 ,  H03F3/45475 ,  H03F3/45928 ,  H03F2200/06 ,  H03F2200/261 ,  H03F2200/78 ,  H03F2203/45138 ,  H03F2203/45594

Abstract: A single-ended to differential conversion circuit for converting an input signal into a pair of differential signals is provided. An amplifier includes an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. A first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. The third resistor is coupled to the output terminal of the amplifier. The resistor string is coupled between the output terminal of the amplifier and the second resistor, and includes a fourth resistor and a fifth resistor connected in series. A signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string.

公开(公告)号：US09537497B2

公开(公告)日：2017-01-03

申请号：US15044125

申请日：2016-02-16

Applicant: MEDIATEK INC.

Inventor： Chen-Yen Ho ,  Yu-Hsin Lin ,  Tze-Chien Wang

IPC: H03M1/00 ,  H03M1/06 ,  H03M3/00

CPC classification number: H03M1/06 ,  H03M3/37 ,  H03M3/422 ,  H03M3/464

Abstract: A continuous time delta sigma modulator includes a summing circuit, a loop filter, an extraction circuit, a quantizer and a digital to analog converter. The summing circuit is arranged for subtracting a feedback signal by an input signal to generate a residual signal. The loop filter includes a plurality of amplifying stages connected in series and is arranged to receive the residual signal to generate a filtered residual signal. The extraction circuit is arranged for extracting a current from one of the amplifying stages and forwarding the extracted current to a following one of the amplifying stages. The quantizer is arranged for generating a digital output signal according to the filtered residual signal. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the digital output signal to generate the feedback signal to the summing circuit.

Abstract translation: 连续时间ΔΣ调制器包括求和电路，环路滤波器，提取电路，量化器和数模转换器。 求和电路被布置为通过输入信号减去反馈信号以产生残余信号。 环路滤波器包括串联连接的多个放大级，并被布置为接收残余信号以产生滤波的残留信号。 提取电路被布置为从一个放大级提取电流，并将提取的电流转发到下一个放大级。 量化器被布置用于根据滤波的残留信号产生数字输出信号。 数模转换器被配置为根据从数字输出信号导出的信号执行数模转换操作，以产生到求和电路的反馈信号。

公开(公告)号：US09007249B2

公开(公告)日：2015-04-14

申请号：US14134944

申请日：2013-12-19

Applicant: MediaTek Inc.

Inventor： Chen-Yen Ho ,  Chi-Lun Lo ,  Hung-Chieh Tsai ,  Yu-Hsin Lin

IPC: H03M3/00 ,  H03F3/45 ,  H03F3/26 ,  H03F3/30

CPC classification number: H03F1/0205 ,  H03F3/265 ,  H03F3/30 ,  H03F3/3023 ,  H03F3/45071 ,  H03F3/45179 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/18 ,  H03F2203/30021 ,  H03F2203/30033 ,  H03F2203/45022 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03M3/39 ,  H03M3/50

Abstract: An amplifier includes a front-end gain stage and an AC-coupled push-pull output stage. The AC-coupled push-pull output stage includes a first transistor, having a source, a drain and a gate, wherein the source of the first transistor is coupled to a first voltage level; a second transistor, having a source, a drain and a gate, wherein the source of the second transistor is coupled to a second voltage level, the gate of the second transistor is coupled to the front-end gain stage, and the drain of the second transistor is coupled to the drain of the first transistor to form an output terminal of the amplifier; an AC-coupled capacitor, which is a passive two terminal electrical component coupled between the front-end gain stage and the gate of the first transistor; and a resistance component, coupling the gate of the first transistor to a bias voltage level.

Abstract translation: 放大器包括前端增益级和AC耦合推挽输出级。 AC耦合推挽输出级包括具有源极，漏极和栅极的第一晶体管，其中第一晶体管的源极耦合到第一电压电平; 具有源极，漏极和栅极的第二晶体管，其中所述第二晶体管的源极耦合到第二电压电平，所述第二晶体管的栅极耦合到所述前端增益级，并且所述漏极 第二晶体管耦合到第一晶体管的漏极，以形成放大器的输出端; AC耦合电容器，其是耦合在前端增益级与第一晶体管的栅极之间的无源双端电气元件; 以及电阻分量，将第一晶体管的栅极耦合到偏置电压电平。

公开(公告)号：US08928511B2

公开(公告)日：2015-01-06

申请号：US13691860

申请日：2012-12-03

Applicant: Mediatek Inc.

Inventor： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

IPC: H03M3/00 ,  H03M7/30

CPC classification number: H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

Abstract translation: Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息。