-
公开(公告)号：US20220217101A1
公开(公告)日：2022-07-07
申请号：US17142366
申请日：2021-01-06
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Gal Yefet , Daniel Marcovitch , Roee Moyal , Ariel Shahar , Gil Bloch , Lior Narkis
IPC: H04L12/879 , H04L12/861 , H04L12/937 , H04L12/24
Abstract: A network adapter includes a network interface, a host interface and processing circuitry. The network interface connects to a communication network for communicating with remote targets. The host interface connects to a host that accesses a Multi-Channel Send Queue (MCSQ) storing Work Requests (WRs) originating from client processes running on the host. The processing circuitry is configured to retrieve WRs from the MCSQ and distribute the WRs among multiple Send Queues (SQs) accessible by the processing circuitry.
-
公开(公告)号：US20210328923A1
公开(公告)日：2021-10-21
申请号：US16853783
申请日：2020-04-21
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Avi Urman , Lior Narkis , Ariel Shahar
IPC: H04L12/743 , H04L12/815
Abstract: In one embodiment, a network device includes an interface configured to receive a data packet including a header section, at least one parser to parse the data of the header section yielding a first header portion and a second header portion, a packet processing engine to fetch a first match-and-action table, match a first index having a corresponding first steering action entry in the first match-and-action table responsively to the first header portion, compute a cumulative lookup value based on the first header portion and the second header portion responsively to the first steering action entry, fetch a second match-and-action table responsively to the first steering action entry, match a second index having a corresponding second steering action entry in the second match-and-action table responsively to the cumulative lookup value, and steering the packet responsively to the second steering action entry.
-
公开(公告)号：US20210286646A1
公开(公告)日：2021-09-16
申请号：US17331657
申请日：2021-05-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ariel Shahar , Roee Moyal
IPC: G06F9/48
Abstract: A method using a memory and queue handling logic, including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C.
-
公开(公告)号：US11055130B2
公开(公告)日：2021-07-06
申请号：US16571122
申请日：2019-09-15
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ariel Shahar , Roee Moyal
Abstract: A method including accessing a work control structure (WCS) configured “first-in-first-out” holding work control records (WCRs) each including a field defining work to be carried out and a completion indicator indicating whether the work has completed, and initially set to indicate that the work has not completed: upon fetching a work request (WR) for execution, pushing a WCR corresponding to the WR to the WCS, and: A) inspecting the WCR at a head of the WCS, B) when the completion indicator of the WCR at the head of the WCS indicates that the unit of work associated with the WCR at the head of the WCS has been completed, popping the WCR at the head of the WCS from the WCS, and reporting completion of the WCR at the head of the WCS to a host processor, and C) iteratively performing A, B, and C. Related apparatus and methods are also provided.
-
公开(公告)号：US20160072906A1
公开(公告)日：2016-03-10
申请号：US14834443
申请日：2015-08-25
Applicant: Mellanox Technologies Ltd.
Inventor： Shahaf Shuler , Noam Bloch , Ofer Hayut , Richard Graham , Ariel Shahar
CPC classification number: H04L67/26 , H04L49/9068 , H04L67/10 , H04L67/1093 , H04L67/1097 , H04L69/06
Abstract: A method for communication includes posting, by a software process, a set of buffers in a memory of a host processor and creating in the memory a list of labels associated respectively with the buffers. The software process pushes a first part of the list to a network interface controller (NIC), while retaining a second part of the list in the memory under control of the software process. Upon receiving a message containing a label, sent over a network, the NIC compares the label to the labels in the first part of the list and, upon finding a match to the label, writes data conveyed by the message to a buffer in the memory. Upon a failure to find the match in the first part of the list, the NIC passes the message from the NIC to the software process for handling using the second part of the list.
Abstract translation: 一种用于通信的方法包括通过软件处理将主机处理器的存储器中的一组缓冲器发布，并在存储器中创建分别与缓冲器相关联的标签的列表。 软件进程将列表的第一部分推送到网络接口控制器（NIC），同时在软件进程控制下将列表的第二部分保留在内存中。 在接收到包含通过网络发送的标签的消息时，NIC将标签与列表的第一部分中的标签进行比较，并且在找到与标签的匹配时，将消息传送的数据写入存储器中的缓冲器 。 如果在列表的第一部分找不到匹配项，则NIC将该消息从NIC传递到软件进程以使用列表的第二部分进行处理。
-
Patent Agency Ranking
公开(公告)号：US12259832B2
公开(公告)日：2025-03-25
申请号：US18174668
申请日：2023-02-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Tzahi Oved , Achiad Shochat , Liran Liss , Noam Bloch , Aviv Heller , Idan Burstein , Ariel Shahar , Peter Paneah
Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.
-
公开(公告)号：US12224950B2
公开(公告)日：2025-02-11
申请号：US17979018
申请日：2022-11-02
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Gal Yefet , Daniel Marcovitch , Roee Moyal , Gil Bloch , Ariel Shahar , Yossef Itigin
IPC: G06F15/16 , H04L47/62 , H04L47/625 , H04L47/6275
Abstract: In one embodiment, a system includes a memory to store a work queue including work queue entry slots, a processing device to write work queue entries to the work queue in a consecutive and cyclic manner, and a network device including a network interface to share packet over a network, and packet processing circuitry to read the work queue entries from the work queue in a consecutive and cyclic manner, the work queue entries indicating work to be performed associated with the packets, dequeue respective ones of the work queue entries read from the work queue responsively to reading the respective work queue entries from the work queue, add the work queue entries to an execution database used to track execution of the work queue entries, and execute the work queue entries in the execution database.
-
公开(公告)号：US20250028658A1
公开(公告)日：2025-01-23
申请号：US18224262
申请日：2023-07-20
Applicant: Mellanox Technologies, Ltd.
Inventor： Ortal Ben Moshe , Roee Moyal , Shay Aisman , Gil Bloch , Ariel Shahar , Roman Nudelman , Gil Kremer , Yossef Itigin , Lior Narkis
Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.
-
公开(公告)号：US20250023668A1
公开(公告)日：2025-01-16
申请号：US18351544
申请日：2023-07-13
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Roee Moyal , Gil Kremer , Ortal Ben Moshe , Ariel Shahar
IPC: H04L1/1607 , H04L1/08 , H04L47/34
Abstract: In one embodiment, a first network device includes a host interface to receive messages from a host device, packet processing circuitry to send a batch of the messages to a second network device without waiting for an acknowledgement receipt from the second network device after sending each message, one message in the batch having a maximum message sequence number (MSN), receive a given acknowledgement receipt from the second network device indicating that all the messages in the batch have been received and including credit data indicating that there is no space in a receive work queue of the second network device for receiving an additional message, and send the additional message having an MSN greater than the maximum MSN to the second network device responsively to receiving the given acknowledgement receipt and based on the credit data indicating that there is no space in the receive work queue.
-
公开(公告)号：US20240394060A1
公开(公告)日：2024-11-28
申请号：US18321013
申请日：2023-05-22
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor： Ariel Shahar , Avi Urman , Omri Kahalon , Uria Basher , Doron Haim , Sagi Farjun
Abstract: A network device includes one or more ports, match-action circuitry, and an action processor. The one or more ports are to exchange packets between the network device and a network. The match-action circuitry is to match at least some of the packets to one or more rules so as to set respective actions to be performed, at least one of the actions including a programmable action. The instruction processor is to perform the programmable action by running user-programmable software code. The instruction processor includes architectural registers, one or more of the architectural registers being accessible by the match-action circuitry, and the match-action circuitry is to write into the architectural registers information for performing the programmable action.
-
-
-
-
-
-
-
-
-
Search Results
95
records
(took 0.023 seconds)
