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    SEGREGATION-BASED MEMORY
    51.
    发明申请
    SEGREGATION-BASED MEMORY 审中-公开

    公开(公告)号：US20200051626A1

    公开(公告)日：2020-02-13

    申请号：US16102493

    申请日：2018-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Agostino Pirovano ,  Innocenzo Tortorelli

    IPC: G11C13/00

    Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.

    Arrays Of Memory Cells And Methods Of Forming An Array Of Elevationally-Outer-Tier Memory Cells And Elevationally-Inner-Tier Memory Cells
    52.
    发明申请
    Arrays Of Memory Cells And Methods Of Forming An Array Of Elevationally-Outer-Tier Memory Cells And Elevationally-Inner-Tier Memory Cells 审中-公开

    公开(公告)号：US20200013829A1

    公开(公告)日：2020-01-09

    申请号：US16575743

    申请日：2019-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24

    Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.

    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
    53.
    发明申请
    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE 审中-公开

    公开(公告)号：US20190362789A1

    公开(公告)日：2019-11-28

    申请号：US16419821

    申请日：2019-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

    IPC: G11C13/00 ,  G11C11/56 ,  H01L27/24

    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

    Three dimensional memory arrays
    54.
    发明授权
    Three dimensional memory arrays 有权

    公开(公告)号：US10461125B2

    公开(公告)日：2019-10-29

    申请号：US15689155

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Andrea Redaelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L27/24 ,  H01L45/00 ,  H01L27/115

    Abstract: In an example, a memory array may include a plurality of first dielectric materials and a plurality of stacks, where each respective first dielectric material and each respective stack alternate, and where each respective stack comprises a first conductive material and a storage material. A second conductive material may pass through the plurality of first dielectric materials and the plurality of stacks. Each respective stack may further include a second dielectric material between the first conductive material and the second conductive material.

    Apparatuses including memory cells and methods of operation of same
    55.
    发明授权
    Apparatuses including memory cells and methods of operation of same 有权

    公开(公告)号：US10157670B2

    公开(公告)日：2018-12-18

    申请号：US15338154

    申请日：2016-10-28

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Innocenzo Tortorelli ,  Andrea Redaelli ,  Fabio Pellizzer

    IPC: G11C11/00 ,  G11C13/00

    Abstract: Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.

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